AI-Driven RTL Power Optimization Engineer

Nvidia Corporation; Santa Clara (CA); On-site; USD 116,000 - 218,500; Full time

Benefits offered by this job

Equity granting

Benefits

Job summary

NVIDIA is seeking a highly skilled engineer to advance RTL power optimization for its data-center, gaming, and automotive GPU and networking chips. You will study power, analyze RTL designs, and collaborate with architects and RTL designers to reduce energy consumption across pre-silicon stages.

The role emphasizes Python scripting, AI/ML methods in EDA, and applying power optimization techniques such as clock gating and multi-VT usage.

Qualifications

• Pursuing or recently completed a MS or PhD in Electrical Engineering, Computer Engineering, or related fields with coursework or experience in AI, Digital Design and VLSI concepts (or equivalent experience).
• Understanding of RTL power optimization fundamentals, including switching activity, clock/enable efficiency, and common low-power design patterns at the RTL level.
• Knowledge of backend flows such as logic synthesis and place-and-route, and how RTL decisions impact post-layout power and timing.
• Familiarity with RTL implementation of low-power techniques (e.g., clock gating, operand isolation, power gating strategies, multi-VT usage) and their trade-offs.
• Exposure to industry power analysis tools such as PowerArtist, PrimeTime PX, or equivalent, including running power analysis and interpreting reports to guide design changes.
• Strong Python programming skills for building automation scripts, data pipelines, and AI/ML-driven analysis flows for RTL power optimization.
• Coursework and/or hands‑on experience in Machine Learning and Artificial Intelligence, with ability to apply ML techniques to EDA and silicon power problems.
• Previous experience debugging RTL or gate‑level power anomalies by tracing logic cones, examining activity/toggle data, and identifying root‑cause structures or scenarios.
• Strong written and verbal communication skills to document methodologies, present power findings, and explain AI/ML-based insights to both design and tools teams.

Responsibilities

• Use internally developed tools and industry standard pre-silicon gate-level and RTL power analysis tools, to help improve product power efficiency.
• Use artificial intelligence to devliver RTL and/or Architecture Power optimization solutions.
• Develop and share best practices for performing pre-silicon power analysis.
• Perform comparative power analysis, to spot trends and anomalies, that warrant more scrutiny.
• Interact with architects and RTL designers to help them interpret their power data and identify power bugs; drive them to implement fixes.
• Select and run a wide variety of workloads for power analysis.
• Prototype a new architectural feature in Verilog and analyze power.

Skills

Python programming

RTL power optimization

Power analysis

ML-driven analysis

AI/ML techniques

Education

MS/PhD in EE/CE or related fields

Tools

PowerArtist

PrimeTime PX

Job description

NVIDIA is seeking a highly skilled engineer to advance RTL power optimization for its data-center, gaming, and automotive GPU and networking chips. You will study power, analyze RTL designs, and collaborate with architects and RTL designers to reduce energy consumption across pre-silicon stages.

The role emphasizes Python scripting, AI/ML methods in EDA, and applying power optimization techniques such as clock gating and multi-VT usage.