Principal CAD/EDA Architect — Design Automation & Infra

Lattice Semiconductor Corp; United States; Sur place; USD 231 000 - 290 000; Plein temps

Avantages offerts par ce poste

Equity

Healthcare

Retirement plans

Paid time off

Résumé du poste

Lattice Semiconductor Corp is seeking a Principal Engineer to lead CAD and EDA infrastructure strategy, architecture, and operations for ASIC/SoC teams. You will drive scalable engineering environments, cloud-enabled design workflows, and productivity initiatives across global groups.

The role requires deep semiconductor design flow knowledge, proficiency with Linux and EDA tools, and strong leadership to mentor engineers and partner with architecture and verification teams.

Qualifications

• Bachelor's or Master’s degree in Electrical/Computer Engineering, Computer Science, or related field.
• 12+ years in semiconductor design methodologies, CAD engineering, or EDA infrastructure.
• Deep understanding of ASIC/SoC design and verification flows.
• Strong Linux/Unix and distributed computing experience.
• Hands-on experience with leading EDA platforms (Synopsys, Cadence).
• Advanced programming skills in Python, Tcl, Shell, or similar.

Responsabilités

• Define vision and strategy for CAD/EDA infrastructure across ASIC, SoC, IP, and verification teams.
• Develop and maintain scalable engineering environments and cloud-enabled workflows.
• Improve tool reliability and user productivity through automation and standards.
• Lead automation with Python/Tcl/Shell; build self-service dashboards and CI/CD for CAD.
• Mentor engineers; guide future investments and resolve complex productivity issues.

Connaissances

Semiconductor design

EDA tooling

Linux/Unix

Python

Automation

CI/CD

DevOps

Compute farms

Stakeholder mgmt

Programming languages

Formation

Bachelor's or Master's in EE/CS

Outils

Synopsys Cadence

Siemens/Mentor

Description du poste

Lattice Semiconductor Corp is seeking a Principal Engineer to lead CAD and EDA infrastructure strategy, architecture, and operations for ASIC/SoC teams. You will drive scalable engineering environments, cloud-enabled design workflows, and productivity initiatives across global groups.

The role requires deep semiconductor design flow knowledge, proficiency with Linux and EDA tools, and strong leadership to mentor engineers and partner with architecture and verification teams.