Electronic Warfare FPGA Engineer: Real-Time DSP Architect

Calico Teknoloji; Çankaya; Presencial; TRY 120.000 - 180.000; Jornada completa

Ventajas ofrecidas por este puesto de trabajo

Health insurance

Fuel support

Descripción de la vacante

Calico Teknoloji seeks an Electronic Warfare FPGA Engineer to implement high‑performance DSP pipelines for SDR, EW/ESM systems on modern FPGA platforms. You will translate DSP concepts into deterministic FPGA architectures and remain hands-on with Python-based prototyping and validation.

The role involves close collaboration with algorithm, RF, and embedded/FPGA teams to deliver real‑time processing chains—from wideband IQ ingestion to detection, parameter extraction, and reporting.

Formación

• Bachelor’s degree in Electrical Engineering or Computer Engineering.
• 2+ years of professional FPGA development experience in DSP, radar, or EW domains.
• Strong DSP theory, SDR architectures, and radar signal processing knowledge.
• Deep understanding of CFAR and hardware implementation constraints.
• Experience with polyphase filters, CIC filters, CORDIC, and FFT pipelines in FPGA.
• Proficiency in Python (NumPy/SciPy) for algorithm development and debugging.
• Ability to translate floating‑point algorithms to fixed‑point HDL implementations.
• Knowledge of FPGA memory architectures (BRAM, URAM, DDR).
• Experience with Ethernet and/or PCIe data movement architectures.

Responsabilidades

• Implement FPGA-based DSP pipelines for SDR, ESM, and EW systems.
• Translate Python and C++ prototypes into synthesizable HDL (VHDL/Verilog/SystemVerilog).
• Optimize fixed-point representations and quantization trade‑offs while preserving performance.
• Implement and optimize: CORDIC, CIC filters, Half‑band filters, Polyphase filter banks, and FFT pipelines.
• Implement detection pipelines with CFAR variants and adaptive thresholding.
• Translate radar and array signal processing concepts into FPGA‑efficient architectures.
• Develop synchronization, pilot-based channel estimation, and Preamble detection blocks.
• Architect streaming pipelines with deterministic latency and high‑speed interfaces (Ethernet/PCIe).
• Debug and validate DSP algorithms in Python and HDL, with golden reference models.

Conocimientos

DSP theory

SDR architectures

Radar signal processing

CFAR

Python (NumPy/SciPy)

HDL (VHDL/Verilog/SystemVerilog)

Educación

Electrical Engineering

Computer Engineering

Herramientas

Verilog

SystemVerilog

HDL simulators

Descripción del empleo

Calico Teknoloji seeks an Electronic Warfare FPGA Engineer to implement high‑performance DSP pipelines for SDR, EW/ESM systems on modern FPGA platforms. You will translate DSP concepts into deterministic FPGA architectures and remain hands-on with Python-based prototyping and validation.

The role involves close collaboration with algorithm, RF, and embedded/FPGA teams to deliver real‑time processing chains—from wideband IQ ingestion to detection, parameter extraction, and reporting.