Electronic Warfare FPGA Engineer - Real-Time DSP Architect

Jobspage; Çankaya; On-site; TRY 180,000 - 260,000; Full time

Job summary

Jobspage seeks an Electronic Warfare FPGA Engineer to implement high-performance DSP pipelines on SDR/EW systems. You will translate Python-based prototypes into synthesizable HDL while optimizing fixed-point representations for resource-efficient hardware.

You will collaborate with algorithm and RF/embedded teams to deliver real-time processing chains from wideband IQ ingestion to detection and reporting on modern FPGA platforms.

Qualifications

• Bachelor's degree required or equivalent in electrical/telecom engineering.
• 2+ years of professional FPGA development in DSP/radar/EW.
• Solid foundation in DSP theory and SDR architectures.
• CFAR and hardware implementation constraints understood.
• Experience translating prototypes into fixed‑point HDL.

Responsibilities

• Implement FPGA-based DSP pipelines for SDR, ESM, and EW systems.
• Translate Python/C++ prototypes into synthesizable HDL (VHDL/Verilog/SystemVerilog).
• Optimize fixed‑point representations and quantization trade‑offs.
• Design memory-efficient FPGA architectures with BRAM/URAM and DDR.
• Develop and validate high-throughput FFT pipelines and PDW/ESM blocks.

Skills

DSP theory

SDR architectures

Radar signal processing

Signal detection theory

Fixed-point hardware

Python (NumPy/SciPy)

HDL design

FPGA memory architectures

CFAR implementation

FFT pipelines

Education

Bachelors in Electrical Engineering or related

Tools

VHDL/Verilog/SystemVerilog

CORDIC

CIC filters

Polyphase filters

PFB

Ethernet/ PCIe interfaces

Job description

Jobspage seeks an Electronic Warfare FPGA Engineer to implement high-performance DSP pipelines on SDR/EW systems. You will translate Python-based prototypes into synthesizable HDL while optimizing fixed-point representations for resource-efficient hardware.

You will collaborate with algorithm and RF/embedded teams to deliver real-time processing chains from wideband IQ ingestion to detection and reporting on modern FPGA platforms.