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Best NanoTech in Singapore seeks an experienced hardware engineer to design, validate and sustain test-interface hardware for wafer sort and final test, collaborating with ATE, PCB, product and packaging teams to deliver robust, high-signal-integrity solutions. Requires 3–10+ years in semiconductor test or related fields, hands-on ATE experience, and strong analytical skills.
English proficiency is essential; the role is on-site in Singapore with opportunities to contribute to NPI and production
Location: Singapore
Experience: 3-10+ years
Mobility: Open to qualified candidates currently based in India who are willing to relocate to Singapore; employment and work authorization subject to employer requirements.
Design, validate and sustain semiconductor test-interface hardware for wafer sort, final test and characterization. The role requires close interaction with ATE, package, product and PCB teams to deliver robust, high-signal-integrity test solutions.
Country-specific emphasis: Experience supporting high-volume outsourced test or engineering services is useful.