Synthesis & STA Engineer — Low-Power & Timing Expert

PICOHEART (SG) PTE. LTD.; Singapore; On-site; SGD 90,000 - 140,000; Full time

Job summary

ByteDance seeks a seasoned IC design engineer to join the Silicon Platform Team, driving logic synthesis, RTL to GDSII flow, timing signoff and low-power implementation across architectures.

You will collaborate with front‑end and back‑end engineers through the full chip design flow, apply UPF, clock gating and DFT concepts, perform formal verification, and support tape-out, mass production, and post‑layout verification to ensure robust, scalable silicon.

Qualifications

• Bachelor's or Master's degree in electrical engineering, computer engineering, or a related field.
• 3+ years of IC design experience focused on sdc, synthesis, timing signoff, low-power implementation.
• Proficiency in Verilog/SystemVerilog, RTL-to-GDSII flow, and EDA tools (Fusion Compiler, Genus/Innovus+, PrimeTime/Tempus, Formality, Conformal LP).

Responsibilities

• Perform logic synthesis and design optimization for architectures and RTLs.
• Timing constraints (SDC) preparation and tuning, and conduct hierarchical/full-chip STA signoff and timing closure.
• Implement low-power design techniques and constraints (UPF, clock gating, power gating, dynamic voltage scaling).
• Formal verification & equivalence checking using formal verification tools (Conformal, Formality).
• Work with front-end engineers for architectural exploration and planning.
• Work with backend engineers on floorplanning, place & route (P&R), congestion analysis, and timing bottlenecks.

Skills

Synthesis

Verilog/SystemVerilog

Timing analysis

DFT methodologies

Education

Bachelor's/Master's in EE/CE

Tools

Fusion Compiler

Genus/Innovus+

PrimeTime/Tempus

Formality

Conformal LP

Job description

ByteDance seeks a seasoned IC design engineer to join the Silicon Platform Team, driving logic synthesis, RTL to GDSII flow, timing signoff and low-power implementation across architectures.

You will collaborate with front‑end and back‑end engineers through the full chip design flow, apply UPF, clock gating and DFT concepts, perform formal verification, and support tape-out, mass production, and post‑layout verification to ensure robust, scalable silicon.