Backend Engineer – Synthesis

AMLOGIC SINGAPORE PRIVATE LIMITED; Singapore; On-site; SGD 90,000 - 120,000; Full time

Job summary

AMLOGIC SINGAPORE PRIVATE LIMITED is seeking a hardware design professional to drive RTL-to-gate synthesis and DFT implementation for complex chips. You will collaborate with RTL, PnR, and FE/BE teams to ensure timing and power integrity across DFT designs.

Responsibilities include SDC creation, DFT tasks including ATPG/MBIST, and coordinating with cross-functional teams to achieve timing closure and robust testing.

Qualifications

• Bachelor’s degree or higher in microelectronics, electronic engineering, or related field.
• Experience with backend design flow and EDA tools (DC/FC/TetraMax preferred).
• Experience with physical implementation/verification for large-scale chips at 28nm or below.

Responsibilities

• Synthesize RTL to gate-level netlist.
• Create and verify SDC with RTL team.
• Improve PPA with PnR engineers for digital modules.
• Perform DFT tasks: synthesis, scan insertion, ATPG, MBIST, boundary scan, and functional testing.
• Collaborate with front-end and back-end teams on DFT-related STA, power, and IR drop analysis for timing closure.

Skills

Communication

Stress management

Teamwork

Education

Bachelor’s degree in Microelectronics/Electronic Engineering

Tools

DC

FC

TetraMax

Job description

Job Responsibilities

• Responsible for synthesis from RTL to gate-level netlist
• Work with RTL design team to create and verify SDC
• Work with PnR engineers to improve PPA of digital modules
• Responsible for the DFT (Design for Test) tasks of the entire chip or module, including synthesis, scan insertion, ATPG, MBIST, boundary scan, and functional testing.
• Collaborate with front-end and back-end teams to perform DFT-related STA, power, and IR drop analysis, ensuring timing closure for DFT designs.

Qualifications

• Bachelor’s degree or higher in Microelectronics, Electronic Engineering, or a related field.
• Familiarity with backend design flow and tools; experience with EDA tools such as DC/FC/TetraMax is preferred.
• Experience in physical implementation and physical verification for large-scale chips at 28nm or below.
• Proficiency in Verilog, TCL, Perl, and Python is a plus.
• Strong communication, stress management, and teamwork skills, with the ability to work effectively in a cross-departmental environment.