Standard Cell Library Engineer

PERSOL SINGAPORE PTE. LTD.; Singapore; On-site; SGD 90,000 - 150,000; Full time

Job summary

PERSOL SINGAPORE PTE. LTD. is seeking an engineering professional to contribute to the development of an advanced design platform for MediaTek multi-vertical projects. You will work on complex circuit blocks, standard cell libraries, and close collaboration with layout and verification teams.

The role emphasizes Python/C/C++ scripting, data analysis and machine learning to optimize performance, power, and timing across FinFet/Nanosheet technologies, with strong teamwork expectations.

Qualifications

• Bachelor/Master's degree in Electrical and Electronic Engineering, Computer Engineering or Computer Science.
• Proficiency in Python, Perl, Tcl or C/C++ for flow development and data analysis, and machine learning.
• Basic knowledge of digital design and/or circuit design.

Responsibilities

• Develop complex circuit blocks from schematic to GDS for leading-edge nodes (planar, finfet, nanosheet).
• Develop standard cell libraries from architecture evaluation, PPA assessment and customized cell design.
• Collaborate with layout engineers for design implementation and physical verification (DRC/LVS/ERC/ANT).
• Perform layout extraction, simulate and analyze data including performance and power for layout-dependent effects.
• Work with digital and testing teams for silicon data collection.
• Develop silicon data analysis flows, visualization and AI model regression.
• Develop advanced library generation methodology including characterization, kit generation and regression.
• Characterize timing, power, constraints, noise and LVF variation for standard cells or blocks.
• Collaborate with circuit designers and tool vendors to tackle modeling challenges and runtime issues.
• Enable and evaluate new kits, such as EM and aging characterization, and engage in data analytics for circuit performance.

Skills

Python

Perl

Tcl

C/C++

Machine learning

Data analysis

Digital design

Teamwork

Education

Bachelor/Master in Electrical and Electronic Engineering/Computer Engineering/Computer Science

Job description

You will be in a energetic team working on advanced technology development, as the pioneer to setup leading edge design platform for MediaTek multi-vertical projects.

• Develop complex circuit block, test key for leading-edge process node (planar, finfet, nanosheet) from schematic netlist to gds.
• Develop standard cell library from architecture evaluation, PPA assessment and customized cell design with different PPA purpose and IP blocks.
• Work with layout engineer for design implementation and physical verification including DRC/LVS/ERC/ANT.
• Perform layout extraction, simulation, analyze simulation data, including performance, power, leakage, for layout dependent effect study.
• Work with digital team and testing team for design implementation and chip level silicon data collection.
• Develop processing flow for silicon data analysis, visualization, AI model regression.
• Develop advanced library generation methodology and flow, including characterization, kit generation, regression, and quality assurance.
• Perform timing/power/constraint/noise/LVF variation characterization for standard cell or complex circuit blocks.
• Work with circuit designer and tool vendors to tackle modelling difficulties, like accuracy and runtime issues, especially for complex circuit blocks.
• Responsible for new kits enablement and evaluation, like EM characterization, aging characterization.
• Involve with data analysis and machine learning as well for circuit performance and power assessment.

Requirement

• Bachelor / Master’s Degree in Electrical and Electronic Engineering/Computer Engineering/Computer Science
• Familiar with Python, Perl, Tcl or C/C++ for flow development and data analysis, machine learning.
• Basic knowledge of digital design and/or circuit design.
• Solid understanding of foundation IP design, with device physics, transistor level circuit, layout dependent effect knowledge.
• Experience of test chip design in FinFet/Nanosheet technologies is a plus, with understanding of DRM, layout rules, PV check, and simulation skills.
• Strong communication and teamwork skills to collaborate effectively with cross-functional teams.