Staff SoC Back-End Implementation Engineer

Silicon Labs; Singapore; Hybrid; SGD 100,440 - 167,400; Full time

Benefits offered by this job

Medical and dental insurance

Bi yearly health screening

Office near Tai Seng MRT

Job summary

Silicon Labs in Singapore is seeking a Staff Implementation Design Engineer to contribute to back-end IC design for highly integrated SoCs for IoT. You will be involved in floorplanning, clock-tree synthesis, power routing, and timing-driven placement and routing.

You will prepare IP data, perform parasitic analysis, rail analysis, and sign-off STA and physical verification, while maintaining PoR flows and evaluating new tools.

Qualifications

• Experience in back-end IC design flows including floorplanning, placement, routing and verification.
• Strong scripting skills in TCL, Python and Perl for flow development.
• Solid understanding of low power design, DFT and CMOS processes.

Responsibilities

• Block and chip level floorplanning, pre-wire and timing-optimization tasks.
• Data preparation of IP like analog and RF macros.
• Detailed place and route for block macros and chip level, including clock-tree-synthesis, power routing, timing-driven placement and routing, SI analysis, and yield techniques.
• Generation of parasitic information.
• Static and dynamic rail analysis.
• Signoff Static Timing Analysis.
• Physical verification including LVS and DRC.
• Maintenance of PnR flows.
• Development of new flow features and tool evaluations.

Skills

Synthesis

Floorplanning

Clock Tree Synthesis

Power Routing & Analysis

Timing Driven Place & Route

Signal Integrity Analysis

Parasitic Generation

Static Timing Analysis

Physical Verification

Design for Test (Scan, ATPG, Memory Bi

Scripting: TCL, Python, Perl

CMOS Low Power

Communication Skills

Education

MS in Electrical Engineering

Job description

Silicon Labs in Singapore is seeking a Staff Implementation Design Engineer to contribute to back-end IC design for highly integrated SoCs for IoT. You will be involved in floorplanning, clock-tree synthesis, power routing, and timing-driven placement and routing.

You will prepare IP data, perform parasitic analysis, rail analysis, and sign-off STA and physical verification, while maintaining PoR flows and evaluating new tools.