Senior/Staff Engineer - HIG HBM PSE

1100 Micron SemiAsiaOP Pte Ltd; Singapore; On-site; SGD 90,000 - 130,000; Full time

Job summary

1100 Micron SemiAsiaOP Pte Ltd is seeking a Validation Lead in Singapore to oversee end-to-end validation runs and develop test programs on industry-leading platforms. The ideal candidate will have over 8 years of experience in DRAM and HBM validation, with strong skills in C/C++ and Verilog simulation.

The role includes high-pressure decision-making, mentoring junior engineers, and collaborating with global teams. A Bachelor’s or Master’s in Electrical or Computer Engineering is required.

Qualifications

• 8+ years in DRAM/HBM/NAND validation or product engineering.
• At least 2 years of HBM validation experience.
• Proven ability to execute ValRuns and perform high-speed I/O validation.

Responsibilities

• Lead end-to-end Validation Run execution in high-pressure environments.
• Deliver decision-ready summary reports by agreed Cycle Time.
• Develop and debug test programs on SM3/Cobra and Advantest V93K.

Skills

DRAM validation

Product engineering

C/C++ programming

Python programming

Verilog simulation

Data analytics

MBIST testing

HBM Validation

Education

Bachelor’s/Master’s in Electrical or Computer Engineering

Tools

Confluence

Jira

Git

Perforce

Job description

Overview

Our vision is to transform how the world uses information to enrich life for all. Join an inclusive team passionate about one thing: using their expertise in the relentless pursuit of innovation for customers and partners. The solutions we build help make everything from virtual reality experiences to breakthroughs in neural networks possible. We do it all while committing to integrity, sustainability, and giving back to our communities. Because doing so can fuel the very innovation we are pursuing.

Key Responsibilities

• Validation Lead: end‑to‑end Validation Run execution in a high‑pressure, fast‑paced environment, ensuring on‑schedule starts/completions, risk‑aware re‑plans, and efficient material usage.
• Own time‑bound data crunching pipelines (automated log parsing, metrics aggregation, anomaly ranking) and deliver decision‑ready summary reports and sightings by agreed Cycle Time.
• Guarantee coverage completeness across MBIST and Native flows; drive Hot/Cold corners, TSV screen/AQLK, async timing boundary coverage, and evidence‑backed closure.
• Platform Leadership: Develop and debug test programs on SM3/Cobra and Advantest V93K; enforce code quality, reviews, and release discipline. Align hardware configs (handler, socket, loadboard, probe card) to test intent and throughput targets.
• Advanced Analysis, Verilog Simulation & Automation: Perform power/thermal characterization; correlate IDD/thermal data with performance/reliability; author recommendations for content changes and silicon fixes. Architect and execute Verilog simulations (bench creation, stimulus, checkers, waveform analysis) to replicate platform sightings, validate hypotheses, and de‑risk content changes before deployment. Build automation scripts and dashboards for anomaly detection, trend analysis, and coverage auditing.
• Debug & Continuous Improvement: Lead silicon debug across Design, Verification, Quality, and System Engineering; drive corrective action closure with clear root‑cause evidence. Implement cycle‑time optimization strategies (parallelization, smarter sampling, content pruning, throughput tuning). Contribute to DFMEA gap closure and codify “Definition of Success” for validation quality.
• Mentorship & Collaboration: Coach junior engineers on validation best practices, platform nuances, simulation methodology, and reporting standards. Partner with global teams (Boise, Folsom, Hyderabad, Taiwan) for material readiness and platform enablement.

Minimum Requirements

• Bachelor’s/Master’s in Electrical or Computer Engineering (or related).
• 8+ years in DRAM/HBM/NAND validation or product engineering.
• At least 2 years of HBM Validation experience.
• Test platform code development in C/C++, Python, and APG (Algorithmic Pattern Generator).
• Strong expertise in MBIST (SM3/Cobra) and Native Mode (Advantest V93K) testing.
• Verilog simulation expertise (bench architecture, stimulus/checkers, waveform/log analysis, correlation to platform behavior).
• Proven ability to execute ValRuns and perform high‑speed I/O validation with eye/IDD characterization.
• Advanced scripting and data analytics skills; Confluence/Jira and Git/Perforce experience.

Preferred Skills

• Linux programming experience; familiarity with UVM and version control systems (Git/SVN).
• Comfortable with lab equipment (oscilloscopes, logic analyzers).
• Experience defining CS/QS shmoo targets, async timing boundaries, and coverage‑driven acceptance criteria.
• Familiarity with automation and ML‑driven validation workflows (e.g., anomaly classifiers, trend predictors).

Equal Employment Opportunity

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status.

Compliance Statement

Micron prohibits the use of child labor and complies with all applicable laws, rules, regulations, and other international and industry labor standards. Micron does not charge candidates any recruitment fees or unlawfully collect any other payment from candidates as consideration for their employment with Micron.