Staff Engineer – HBM PE Component Validation (Singapore)

Micron Technology, Inc.; Singapore; Sur place; SGD 100 000 - 130 000; Plein temps

Résumé du poste

Dormont Manufacturing Co in Singapore is seeking a Validation Engineer to lead end-to-end validation runs in a high-pressure environment. The ideal candidate will have over 8 years of experience in DRAM/HBM/NAND validation, and at least 2 years in HBM Validation.

The role demands strong skills in C/C++, Python, and Verilog simulation, alongside expertise in the SM3/Cobra and Advantest V93K testing platforms. Join our dedicated team to drive innovation in technology and engineering.

Qualifications

• 8+ years in DRAM/HBM/NAND validation or product engineering.
• At least 2 years of HBM Validation experience.
• Strong expertise in MBIST and Advantest testing.
• Proven ability to execute ValRuns and perform high-speed I/O validation.

Responsabilités

• Lead Validation Run execution in a fast-paced environment.
• Develop and debug test programs on SM3/Cobra and Advantest V93K.
• Perform power/thermal characterization and build automation scripts.
• Lead silicon debug across Design, Verification, Quality, and System Engineering.
• Coach junior engineers on validation best practices.

Connaissances

DRAM/HBM/NAND validation

Test platform code development in C/C++

Python

Verilog simulation

Data analytics

Confluence/Jira

Git/Perforce

Formation

Bachelor's/Master's in Electrical or Computer Engineering

Outils

SM3/Cobra

Advantest V93K

Description du poste

Our vision is to transform how the world uses information to enrich life for all.

Join an inclusive team passionate about one thing: using their expertise in the relentless pursuit of innovation for customers and partners. The solutions we build help make everything from virtual reality experiences to breakthroughs in neural networks possible. We do it all while committing to integrity, sustainability, and giving back to our communities. Because doing so can fuel the very innovation we are pursuing.

Key Responsibilities

• Validation Execution
  • Lead end‑to‑end Validation Run execution in a high‑pressure, fast‑paced environment , ensuring on‑schedule starts/completions , risk‑aware re‑plans , and efficient IQP/ETV material usage.
  • Own time‑bound data crunching pipelines (automated log parsing, metrics aggregation, anomaly ranking) and deliver decision‑ready summary reports and sightings by agreed Cycle Time.
  • Guarantee coverage completeness across MBIST and flows; drive Hot/Cold corners , TSV screen/AQLK , async timing boundary coverage, and evidence‑backed closure.
• Platform Leadership
  • Develop and debug test programs on SM3/Cobra and Advantest V93K ; enforce code quality, reviews, and release discipline.
  • Align hardware configs ( handler, socket, loadboard, probe card ) to test intent and throughput targets.
• Advanced Analysis, Verilog Simulation & Automation
  • Perform power/thermal characterization ; correlate IDD/thermal data with performance/reliability; author recommendations for content changes and silicon fixes.
  • Architect and execute Verilog simulations (bench creation, stimulus, checkers, waveform analysis) to replicate platform sightings, validate hypotheses, and de‑risk content changes before deployment.
  • Build automation scripts and dashboards for anomaly detection, trend analysis, and coverage auditing.
• Debug & Continuous Improvement
  • Lead silicon debug across Design, Verification, Quality, and System Engineering ; drive corrective action closure with clear root‑cause evidence.
  • Implement cycle‑time optimization strategies (parallelization, smarter sampling, content pruning, throughput tuning).
  • Contribute to DFMEA gap closure and codify “ Definition of Success ” for validation quality.
• Mentorship & Collaboration
  • Coach junior engineers on validation best practices, platform nuances, simulation methodology , and reporting standards.
  • Partner with global teams (Boise, Folsom, Hyderabad, Taiwan) for material readiness and platform enablement.

Minimum Requirements

• Bachelor’s/Master’s in Electrical or Computer Engineering (or related).
• 8+ years in DRAM/HBM/NAND validation or product engineering.
• At least 2 years of HBM Validation experience.
• Test platform code development in C/C++ , Python , and APG (Algorithmic Pattern Generator).
• Strong expertise in MBIST (SM3/Cobra) and Mode (Advantest V93K) testing.
• Verilog simulation expertise (bench architecture, stimulus/checkers, waveform/log analysis, correlation to platform behavior).
• Proven ability to execute ValRuns and perform high‑speed I/O validation with eye/IDD characterization.
• Advanced scripting and data analytics skills; Confluence/Jira and Git/Perforce experience.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status.

To request assistance with the application process and/or for reasonable accommodations, please contact [e-mail].