Staff Engineer – HBM PE Component Validation (Singapore)

Micron; Singapore; On-site; SGD 110,000 - 180,000; Full time

Job summary

Micron Technology, Inc. seeks a seasoned Validation Lead to drive end-to-end validation across memory platforms. You will own data pipelines, build Verilog simulations, and align test hardware to meet throughput and coverage targets.

The role emphasizes silicon debug, DFMEA input, and cross-team collaboration for rapid content validation. You will mentor junior engineers, work with AI-assisted tooling for analysis, and partner with global teams to ensure material readiness and platform

Qualifications

• Bachelor’s/Master’s in Electrical or Computer Engineering (or related).
• 8+ years in DRAM/HBM/NAND validation or product engineering.
• At least 2 years of HBM Validation experience.
• Test platform code development in C/C++, Python, and APG (Algorithmic Pattern Generator).
• Strong expertise in ATE like Advantest and Teradyne Verilog simulation expertise (bench architecture, stimulus/checkers, waveform/log analysis, correlation to platform behavior).
• Proven ability to execute Validations and perform high-speed I/O validation with eye/IDD characterization.
• Advanced scripting and data analytics skills; Confluence/Jira and Git/Perforce experience.
• Strong Analog and Digital Circuit Understanding

Responsibilities

• Validation Execution Lead end-to-end validation run execution in a high-pressure, fast-paced environment, ensuring on-schedule starts/completions, risk-aware re-plans, and efficient material usage.
• Own time-bound data crunching pipelines (automated log parsing, metrics aggregation, anomaly ranking) and deliver decision-ready summary reports and sightings by agreed Cycle Time.
• Guarantee coverage completeness across Validation flows; drive Hot/Cold corners, screen, timing boundary coverage, and evidence-backed closure.
• Develop and debug test programs on ATEs like Advantest and in-house ATE; enforce code quality, reviews, and release discipline.
• Align hardware configs (handler, socket, loadboard, probe card) to test intent and throughput targets.
• Perform power/thermal characterization; correlate IDD/thermal data with performance/reliability; author recommendations for content changes and silicon fixes.
• Architect and execute Verilog simulations (bench creation, stimulus, checkers, waveform analysis) to replicate platform sightings, validate hypotheses, and de-risk content changes before deployment.
• Build automation scripts and dashboards for anomaly detection, trend analysis, and coverage auditing.
• Lead silicon debug across Design, Verification, Quality, and System Engineering; drive corrective action closure with clear root-cause evidence.
• Implement cycle-time optimization strategies (parallelization, smarter sampling, content pruning, throughput tuning).
• Contribute to DFMEA gap closure and codify "Definition of Success" for validation quality.
• Familiar with AI tools and leveraging AI tools to improve productivity, code development, data analysis etc.
• Coach junior engineers on validation best practices, platform nuances, simulation methodology, and reporting standards.
• Partner with global teams for material readiness and platform enablement.

Skills

C/C++ development

Python scripting

Verilog simulation

Data analytics

Git/Perforce

High-speed I/O validation

Confluence/Jira

Analog and digital understanding

Education

Electrical or Computer Engineering (Bachelor/Master)

Tools

Advantest

Teradyne

APG (Algorithmic Pattern Generator)

Job description

Our vision is to transform how the world uses information to enrich life for all. Join an inclusive team passionate about one thing: using their expertise in the relentless pursuit of innovation for customers and partners. The solutions we build help make everything from virtual reality experiences to breakthroughs in neural networks possible. We do it all while committing to integrity, sustainability, and giving back to our communities. Because doing so can fuel the very innovation we are pursuing.

Key Responsibilities

• Validation Execution Lead end‑to‑end Validation Run execution in a high‑pressure, fast‑paced environment, ensuring on‑schedule starts/completions, risk‑aware re‑plans, and efficient material usage.
• Own time‑bound data crunching pipelines (automated log parsing, metrics aggregation, anomaly ranking) and deliver decision‑ready summary reports and sightings by agreed Cycle Time.
• Guarantee coverage completeness across Validation flows; drive Hot/Cold corners, screen, timing boundary coverage, and evidence‑backed closure.

Platform Leadership

• Develop and debug test programs on ATEs like Advantest and In‑house ATE; enforce code quality, reviews, and release discipline.
• Align hardware configs (handler, socket, loadboard, probe card) to test intent and throughput targets.

Advanced Analysis, Verilog Simulation & Automation

• Perform power/thermal characterization; correlate IDD/thermal data with performance/reliability; author recommendations for content changes and silicon fixes.
• Architect and execute Verilog simulations (bench creation, stimulus, checkers, waveform analysis) to replicate platform sightings, validate hypotheses, and de‑risk content changes before deployment.
• Build automation scripts and dashboards for anomaly detection, trend analysis, and coverage auditing.

Debug & Continuous Improvement

• Lead silicon debug across Design, Verification, Quality, and System Engineering; drive corrective action closure with clear root‑cause evidence.
• Implement cycle‑time optimization strategies (parallelization, smarter sampling, content pruning, throughput tuning).
• Contribute to DFMEA gap closure and codify "Definition of Success" for validation quality.
• Familiar with AI tools and leveraging AI tools to improve productivity, code development, data analysis etc.

Mentorship & Collaboration

• Coach junior engineers on validation best practices, platform nuances, simulation methodology, and reporting standards.
• Partner with global teams for material readiness and platform enablement.

Minimum Requirements

• Bachelor’s/Master’s in Electrical or Computer Engineering (or related).
• 8+ years in DRAM/HBM/NAND validation or product engineering.
• At least 2 years of HBM Validation experience.
• Test platform code development in C/C++, Python, and APG (Algorithmic Pattern Generator).
• Strong expertise in ATE like Advantest and Teradyne Verilog simulation expertise (bench architecture, stimulus/checkers, waveform/log analysis, correlation to platform behavior).
• Proven ability to execute Validations and perform high‑speed I/O validation with eye/IDD characterization.
• Advanced scripting and data analytics skills; Confluence/Jira and Git/Perforce experience.
• Strong Analog and Digital Circuit Understanding

About Micron Technology, Inc. We are an industry leader in innovative memory and storage solutions transforming how the world uses information to enrich life for all. With a relentless focus on our customers, technology leadership, and manufacturing and operational excellence, Micron delivers a rich portfolio of high‑performance DRAM, NAND, and NOR memory and storage products through our Micron® and Crucial® brands. Every day, the innovations that our people create fuel the data economy, enabling advances in artificial intelligence and 5G applications that unleash opportunities — from the data center to the intelligent edge and across the client and mobile user experience. To learn more, please visit micron.com/careers

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status.

Micron Prohibits the use of child labor and complies with all applicable laws, rules, regulations, and other international and industry labor standards.

Micron does not charge candidates any recruitment fees or unlawfully collect any other payment from candidates as consideration for their employment with Micron.