Staff Design Verification Engineer – SoC & Edge AI

AMBIQ MICRO SINGAPORE PRIVATE LTD.; Singapore; Sur place; SGD 150 000 - 190 000; Plein temps

Résumé du poste

Ambiq is seeking an experienced hardware verification engineer to verify digital and mixed-signal designs, including SoCs with multiple CPUs, DSPs, security hardware, and IoT-focused logic. You will own DV tasks, develop block- and chip-level test plans, and run full-chip and module verification in a fast-moving environment.

Required are 7–10+ years in verification, strong SystemVerilog (UVM), C/C++, and experience with ARM/RISC-V, AMBA protocols, and low-power CPF/UPF techniques.

Qualifications

• Degree in electrical engineering or related field with strong verification background.
• Extensive experience in block, sub-system and full-chip verification.
• Proficient in SystemVerilog/UVM and C/C++

Responsabilités

• Take ownership of DV tasks and deliver high-quality results.
• Develop test plans at block, sub-system and chip levels.
• Perform SoC-based verification at full-chip and module levels.
• Work with ARM or RISC-V MCU designs and low-power verification.
• Apply CPF/UPF power-aware techniques in verification.
• Create C-based libraries and tests for verification.
• Build scalable test benches using SystemVerilog and UVM.
• Develop comprehensive test cases, stimuli, and checkers for high coverage.
• Automate test environments for randomized testing and scoreboarding.
• Use advanced debugging to fix design and verification issues.
• Do root-cause analysis with design teams to fix issues.
• Track functional and coverage metrics to ensure quality.
• Ensure verification meets project standards; edge AI is preferred.

Connaissances

SystemVerilog

UVM

C/C++

Python

ARM M/RISC-V

Formation

BSEE/MSEE

Outils

AMBA AXI/AHB/APB

CPF/UPF Low Power

3rd party IP integration

Description du poste

Ambiq is seeking an experienced hardware verification engineer to verify digital and mixed-signal designs, including SoCs with multiple CPUs, DSPs, security hardware, and IoT-focused logic. You will own DV tasks, develop block- and chip-level test plans, and run full-chip and module verification in a fast-moving environment.

Required are 7–10+ years in verification, strong SystemVerilog (UVM), C/C++, and experience with ARM/RISC-V, AMBA protocols, and low-power CPF/UPF techniques.