Design Verification Engineer

BLACK SESAME TECHNOLOGIES (SINGAPORE) PTE. LTD.; Singapore; On-site; SGD 70,000 - 120,000; Full time

Job summary

Black Sesame Technologies is seeking engineers to join the design verification team, focusing on next-generation automotive SoCs. You will develop verification platforms and test cases, promote FPV, and perform RTL and gate-level simulations while debugging failures.

The role emphasizes curiosity, self-drive, and collaborative problem solving in a fast-paced hardware environment. Masters or PhD candidates in EE/CE/CS with internship or project experience are welcome; proficiency in SystemVerilog

Qualifications

• Master’s or PhD in Electrical/Computer Engineering or Computer Science.
• Internship or project experience in chip design/verification preferred; fresh graduates with coursework acceptable.
• Proficiency in SystemVerilog and scripting languages (Python, Perl or Shell).
• Strong analytical and debugging skills; good team collaboration.

Responsibilities

• Develop verification platforms and test cases using SystemVerilog and UVM according to verification plans.
• Promote and implement FPV for relevant design modules.
• Perform RTL and gate-level simulation and run regression tests.
• Analyze code and coverage to close gaps; contribute improvements to verification methodologies.

Skills

SystemVerilog

UVM

Python

Perl

Shell scripting

Debugging

Teamwork

Education

Master’s or PhD in Electrical Engineering / Computer Engineering / Computer Science

Job description

Position Overview:

Black Sesame Technologies is seeking motivated and detail-oriented individuals to join our team as Engineer, Design Verification. This is a great opportunity to be part of a fast-paced environment working on next-generation automotive SoCs. You will be involved in developing industry-grade verification platforms and methodologies to ensure our chips meet the highest functional and quality standards. We're looking for candidates who are curious, self-driven, and passionate about hardware verification.

Responsibilities:

• Develop verification platforms and test cases using SystemVerilog and UVM based on verification plans.
• Promote and implement Formal Property Verification (FPV) for relevant design modules.
• Perform RTL and gate-level simulation, execute regression tests, and debug failures.
• Analyze code and functional coverage to identify and close coverage gaps.
• Contribute ideas and improvements to enhance verification methodologies and processes.

Qualification/ Requirements:

• Education: Master’s or PhD degree in Electrical Engineering, Computer Engineering, Computer Science, or related fields.
• Experience: Internship or project experience in chip design/verification preferred. Open to fresh graduates with relevant coursework or research experience.
• Programming Skills: Proficiency in SystemVerilog and scripting languages such as Python, Perl, or Shell.
• Problem-Solving: Strong analytical and debugging skills; ability to work through complex technical challenges.
• Teamwork: Collaborative mindset with strong communication skills and willingness to learn in a fast-paced team environment.