SoC DFT Engineer – Test & Verification Expert

Avago Technologies Intl' Sales Pte Ltd; Singapore; On-site; SGD 60,000 - 100,000; Full time

Job summary

Avago Technologies Intl' Sales Pte Ltd is seeking a Design-for-Test (DFT) Engineer to join our SoC/ASIC DFT team. You will implement and verify DFT solutions across complex designs, with hands-on DFT insertion and comprehensive verification to ensure first-pass silicon success.

Collaborate with physical design and ATE teams to develop efficient test strategies, generate ATPG patterns, and support silicon bring-up and production test debugging. Strong scripting in TCL/Perl/Python is required.

Qualifications

• Bachelor’s or master’s degree in electrical engineering, computer engineering, or related field.
• Minimum 1 year of experience in DFT design and verification.
• Strong understanding of scan-based test architectures, test compression, and hierarchical DFT implementation.
• Hands-on experience with DFT tools such as Siemens Tessent.

Responsibilities

• Develop and implement DFT architectures for hierarchical SoC and ASIC designs, including block-level and top-level DFT integration.
• Perform scan insertion, test point insertion, and test compression using SSN or equivalent compression architectures.
• Validate SSN topology, managing scan chain balancing and clock-domain crossings.
• Integrate Boundary Scan (IEEE 1149.x) and other test access mechanisms for chip-level testability.
• Generate and analyze ATPG patterns for stuck-at, transition, and path delay faults to ensure good test coverage.
• Perform DFT verification, including Verilog / gate-level simulation.
• Collaborate with cross-functional teams to resolve DFT/testing timing challenges.
• Coordinate with ATE engineers to prepare timing and pattern files (STIL/WGL) for tester compatibility.
• Support silicon bring-up, production test debugging through diagnostics and failure analysis.

Skills

DFT

Scan insertion

ATPG

TCL scripting

Education

Bachelor’s or Master’s in Electrical/Computer Eng

Tools

Siemens Tessent

Verilog

Job description

Avago Technologies Intl' Sales Pte Ltd is seeking a Design-for-Test (DFT) Engineer to join our SoC/ASIC DFT team. You will implement and verify DFT solutions across complex designs, with hands-on DFT insertion and comprehensive verification to ensure first-pass silicon success.

Collaborate with physical design and ATE teams to develop efficient test strategies, generate ATPG patterns, and support silicon bring-up and production test debugging. Strong scripting in TCL/Perl/Python is required.