DFT Engineer

ARETE RESOURCES PTE. LTD.; Singapore; On-site; SGD 90,000 - 130,000; Full time

Job summary

ARETE RESOURCES PTE. LTD. is seeking a motivated Design-for-Test (DFT) Engineer to drive DFT insertion and verification for complex SoC/ASIC designs. The role involves hands-on DFT implementation and comprehensive verification to support first-pass silicon success.

You will collaborate with Physical design and ATE test teams to develop robust test strategies, timing, and pattern validation across TT/production environments.

Qualifications

• Bachelor’s or master’s degree in EE/CE or related field.
• Minimum 3 years of experience in DFT design and verification (5+ years for senior roles).
• Strong understanding of scan-based test architectures, test compression, and hierarchical DFT implementation.
• Hands-on experience with DFT tools such as Siemens Tessent.
• Proficiency in ATPG generation, fault coverage analysis, and gate-level DFT verification.
• Familiarity with ATE test flows and pattern validation on Advantest or Teradyne.
• Strong scripting skills in TCL, Perl, or Python for DFT automation.

Responsibilities

• Develop and implement DFT architectures for hierarchical SoC and ASIC designs, including block- and top-level DFT integration.
• Perform scan insertion, test point insertion, and test compression using SSN or equivalent compression architectures.
• Validate Serial Stream Network (SSN) topology, managing scan chain balancing, clock domain crossings.
• Integrate Boundary scan (IEEE 1149.x) and other test access mechanisms for chip-level testability.
• Generate and analyze ATPG patterns for stuck-at, transition, and path delay faults to ensure optimal test coverage.
• Perform DFT verification, including verilog / gate level simulation.
• Work closely with cross-functional teams to resolve DFT/testing timing challenges.
• Collaborate with ATE engineers to prepare and validate timing and pattern files (STIL/WGL) for tester compatibility and production readiness.
• Support silicon bring-up, production test debugging through diagnostics and failure analysis.

Skills

DFT design

DFT verification

Scripting (TCL/Perl/Python)

ATPG

Education

Bachelor’s or Master’s degree in Electrical/Computer Engineering or related field

Tools

Siemens Tessent

Advantest

Teradyne

Job description

Role Summary

We are seeking a highly motivated Design-for-Test (DFT) Engineer to join our SoC/ASIC DFT development team. The successful candidate will be responsible for implementing and verifying DFT solutions across complex hierarchical designs. This position involves hands-on work in DFT insertion, and comprehensive DFT verification to ensure first-pass silicon success. You will collaborate closely with Physical design team, ATE test teams to develop efficient, high-quality test strategies aligned with industry standards.

Key Responsibilities

• Develop and implement DFT architectures for hierarchical SoC and ASIC designs, including both block-level and top-level DFT integration.
• Perform scan insertion, test point insertion, and test compression using SSN or equivalent compression architectures.
• Validate Serial Stream Network (SSN) topology, managing scan chain balancing, clock domain crossings.
• Integrate Boundary scan (IEEE 1149.x) and other test access mechanisms for chip-level testability.
• Generate and analyze ATPG patterns for stuck-at, transition, and path delay faults to ensure optimal test coverage.
• Perform DFT verification, including verilog / gate level simulation
• Work closely with cross-functional teams to resolve DFT/testing timing challenges.
• Collaborate with ATE engineers to prepare and validate timing and pattern files (STIL/WGL) for tester compatibility and production readiness.
• Support silicon bring-up, production test debugging through Diagnostics and failure analysis.

Qualifications

• Bachelor’s or master’s degree in electrical engineering, Computer Engineering, or related field.
• Minimum 3 years of experience in DFT design and verification (5+ years preferred for senior roles).
• Strong understanding of scan-based test architectures, test compression, and hierarchical DFT implementation.
• Hands-on experience with DFT tools such as Siemens Tessent.
• Proficiency in ATPG generation, fault coverage analysis, and gate-level DFT verification.
• Familiarity with ATE test flows and pattern validation on platforms such as Advantest or Teradyne.
• Strong scripting skills in TCL, Perl, or Python for DFT automation.