SerDes Verification Engineer

XILINX ASIA PACIFIC PTE. LTD.; Singapore; On-site; SGD 90,000 - 120,000; Full time

Job summary

Xilinx Asia Pacific is seeking a SerDes Verification Engineer to verify high-speed SerDes interfaces and testbenches, ensuring protocol compliance and robust performance. You will build UVM/SystemVerilog testbenches, run simulations, and collaborate with hardware teams to resolve timing/protocol issues.

Familiarity with UCIe, PCIe, DDR, and related standards is required. The role emphasizes automation, regression testing, and thorough documentation of verification results, with opportunities to

Qualifications

• Experience in SerDes verification or high-speed communication verification.
• Strong hands-on experience with verification methodologies such as UVM, SystemVerilog, or other simulation-based verification tools.
• Knowledge of high-speed SerDes protocols (UCIe, PCIe, Ethernet, USB, DDR) and related test benches.
• Ability to analyze signal integrity issues, jitter, BER, and eye diagrams.
• Exposure to DDR protocol (DDR3/4/5) for memory interface verification.

Responsibilities

• Verification of SerDes designs: develop and execute verification plans and testbenches for SerDes IPs and subsystems; drive formal verification and assertions.
• Testbench development: design and implement verification testbenches using industry-standard methodologies (UVM, SystemVerilog, VHDL).
• Simulation and debugging: perform simulations, analyze results, and debug timing and protocol issues in SerDes blocks.
• Performance evaluation: evaluate jitter, BER, eye diagrams, signal integrity, and other metrics.
• Protocol compliance testing: verify adherence to SerDes protocols including UCIe, PCIe, Ethernet, USB, DDR, DisplayPort, or custom protocols.
• Automated testing: develop automated regression tests to ensure robustness across versions.
• Collaboration: work with design/hardware/software teams to troubleshoot issues and verify changes.
• Documentation: create reports and documentation on verification results and test scenarios.
• Continuous improvement: provide feedback for verification process improvements and innovate testing strategies.

Skills

Verification expertise

Testbench development

Simulation debugging

Timing/protocol debugging

Performance evaluation

Protocol compliance

Automated testing

Cross-functional collaboration

Documentation

Continuous improvement

HDL familiarity

Scripting (Python/Perl)

Education

Bachelor's or Master's in Computer/Electrical Engineering

Tools

SystemVerilog

UVM

VHDL

Verilog

Python

Perl

Job description

THE ROLE:

You will work on verifying and validating high-speed interfaces used in advanced SoCs and chiplet designs. The role involves building UVM/SystemVerilog testbenches, running simulations, debugging timing and protocol issues, and evaluating signal integrity, jitter, BER, and eye diagrams. Close collaboration with design and hardware teams ensures compliance with protocols such as UCIe, PCIe, and DDR, delivering reliable, high-performance silicon.

THE PERSON:

As a SerDes Verification Engineer, you will be responsible for the verification and validation of high-speed SerDes interfaces, including testing signal integrity, performance, and protocol compliance. You will work closely with hardware and design teams to ensure that SerDes designs meet the required specifications, operating parameters, and quality standards.

KEY RESPONSIBILITIES:

• Verification of SerDes Designs: Develop and execute verification plans and testbenches for SerDes IPs (Intellectual Property) and subsystems to ensure they meet functional and performance requirements. Drive formal verification for the block and write formal properties andassertions to verify the design.


• Testbench Development:Design and implement verification testbenches using industry-standard verification methodologies (e.g., UVM, SystemVerilog, VHDL).


• Simulation and Debugging:Perform simulations, analyze results, and debug issues related to timing, protocol errors, and other design anomalies in SerDes blocks.


• Performance Evaluation:Evaluate and validate performance characteristics of SerDes systems including jitter, bit error rates (BER), signal integrity, eye diagrams, and other key metrics.


• Protocol Compliance Testing:Verify adherence to relevant SerDes protocols such as UCIe, PCIe, Ethernet, USB, DDR, DisplayPort, or custom protocols.


• Automated Testing:Develop automated regression tests to ensure the robustness and stability of the SerDes design over multiple versions and iterations.


• Collaboration:Work closely with the design, hardware, and software teams to troubleshoot issues, implement fixes, and verify design changes.


• Documentation:Create detailed reports and documentation on verification results, test scenarios, and issues found during testing.


• Continuous Improvement:Provide feedback for design and verification process improvements and contribute to innovation in verification strategies and methodologies.

PREFERRED EXPERIENCE:

• Experience in SerDes verification or high-speed communication verification.


• Strong hands‑on experience with verification methodologies such as UVM, SystemVerilog, or other simulation-based verification tools.


• Knowledge of high-speed serial protocols such as UCIe, PCIe, Ethernet, USB, DDR, or custom protocols.


• Experience in analyzing and interpreting signal integrity issues, jitter, BER, and eye diagrams.


• Solid understanding of SerDes architectures, link training, and equalization.


• Strong debugging skills, with the ability to work across multiple domains (timing, protocol, performance).


• Familiarity with hardware description languages (HDL) like VHDL or Verilog.


• Strong analytical, problem‑solving, and communication skills.


• Experience with DDR protocol(e.g., DDR3, DDR4, DDR5) for memory interface verification.


• Understanding of UCIe protocoland its role in chiplet-to-chiplet communication.


• Experience with Python, Perl, or similar scripting languages for automation.


• Exposure to high-speed memory interface design and verification, including DDR controller IP verification.


• Ability to work in a fast‑paced environment and manage multiple verification tasks.

ACADEMIC CREDENTIALS:

• Bachelors or Masters degree in computer engineering/Electrical Engineering

LOCATION:

Singapore