High-Speed SerDes Verification Engineer

XILINX ASIA PACIFIC PTE. LTD.; Singapore; On-site; SGD 90,000 - 120,000; Full time

Job summary

Xilinx Asia Pacific is seeking a SerDes Verification Engineer to verify high-speed SerDes interfaces and testbenches, ensuring protocol compliance and robust performance. You will build UVM/SystemVerilog testbenches, run simulations, and collaborate with hardware teams to resolve timing/protocol issues.

Familiarity with UCIe, PCIe, DDR, and related standards is required. The role emphasizes automation, regression testing, and thorough documentation of verification results, with opportunities to

Qualifications

• Experience in SerDes verification or high-speed communication verification.
• Strong hands-on experience with verification methodologies such as UVM, SystemVerilog, or other simulation-based verification tools.
• Knowledge of high-speed SerDes protocols (UCIe, PCIe, Ethernet, USB, DDR) and related test benches.
• Ability to analyze signal integrity issues, jitter, BER, and eye diagrams.
• Exposure to DDR protocol (DDR3/4/5) for memory interface verification.

Responsibilities

• Verification of SerDes designs: develop and execute verification plans and testbenches for SerDes IPs and subsystems; drive formal verification and assertions.
• Testbench development: design and implement verification testbenches using industry-standard methodologies (UVM, SystemVerilog, VHDL).
• Simulation and debugging: perform simulations, analyze results, and debug timing and protocol issues in SerDes blocks.
• Performance evaluation: evaluate jitter, BER, eye diagrams, signal integrity, and other metrics.
• Protocol compliance testing: verify adherence to SerDes protocols including UCIe, PCIe, Ethernet, USB, DDR, DisplayPort, or custom protocols.
• Automated testing: develop automated regression tests to ensure robustness across versions.
• Collaboration: work with design/hardware/software teams to troubleshoot issues and verify changes.
• Documentation: create reports and documentation on verification results and test scenarios.
• Continuous improvement: provide feedback for verification process improvements and innovate testing strategies.

Skills

Verification expertise

Testbench development

Simulation debugging

Timing/protocol debugging

Performance evaluation

Protocol compliance

Automated testing

Cross-functional collaboration

Documentation

Continuous improvement

HDL familiarity

Scripting (Python/Perl)

Education

Bachelor's or Master's in Computer/Electrical Engineering

Tools

SystemVerilog

UVM

VHDL

Verilog

Python

Perl

Job description

Xilinx Asia Pacific is seeking a SerDes Verification Engineer to verify high-speed SerDes interfaces and testbenches, ensuring protocol compliance and robust performance. You will build UVM/SystemVerilog testbenches, run simulations, and collaborate with hardware teams to resolve timing/protocol issues.

Familiarity with UCIe, PCIe, DDR, and related standards is required. The role emphasizes automation, regression testing, and thorough documentation of verification results, with opportunities to