Staff Engineer - SerDes Verification

XILINX ASIA PACIFIC PTE. LTD.; Singapore; On-site; SGD 120,000 - 180,000; Full time

Job summary

XILINX ASIA PACIFIC PTE. LTD. is seeking a SerDes Verification Engineer in Singapore to verify high‑speed SerDes interfaces, run simulations, and debug timing and protocol issues.

You will assess signal integrity, jitter, BER, and eye diagrams while ensuring compliance with UCIe, PCIe and DDR protocols. Collaborating with design and hardware teams, you will develop verification plans, write testbenches, and drive formal verification.

Qualifications

• Bachelor's or Master's degree in Computer Engineering or Electrical Engineering.
• Experience in SerDes verification or high-speed communication verification.
• Strong knowledge of UVM and SystemVerilog verification methods.

Responsibilities

• Develop and execute verification plans and testbenches for SerDes IPs and subsystems.
• Drive formal verification and write properties and assertions.
• Design and implement verification testbenches using UVM/SystemVerilog.
• Run simulations, analyze results and debug timing/protocol issues.
• Evaluate performance metrics like jitter, BER, eye diagrams and SI.
• Collaborate with design, hardware and software teams to verify changes and document results.

Skills

SerDes verification

UVM/SystemVerilog

High-speed protocols

Signal integrity analysis

Debugging across domains

HDL: VHDL/Verilog

Scripting: Python/Perl

Education

Bachelor's or Master's in Computer/Electrical Engineering

Tools

UVM

SystemVerilog

VHDL/Verilog

Job description

THE ROLE:

The role involves building UVM/SystemVerilog testbenches, running simulations, debugging timing and protocol issues, and evaluating signal integrity, jitter, BER, and eye diagrams. Close collaboration with design and hardware teams ensures compliance with protocols such as UCIe, PCIe, and DDR, delivering reliable, high‑performance silicon.

THE PERSON:

As a SerDes Verification Engineer , you will be responsible for the verification and validation of high-speed SerDes interfaces, including testing signal integrity, performance, and protocol compliance. You will work closely with hardware and design teams to ensure that SerDes designs meet the required specifications, operating parameters, and quality standards. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems.

KEY RESPONSIBILITIES:

• Verification of SerDes Designs: Develop and execute verification plans and testbenches for SerDes IPs (Intellectual Property) and subsystems to ensure they meet functional and performance requirements.
• Drive formal verification for the block and write formal properties and assertions to verify the design. Estimate the time required to write the new feature tests and any required changes to the test environment. Build the directed and random verification tests. Review functional and code coverage metrics - modify or add tests or constrain random tests to meet the coverage requirements.
• Testbench Development: Design and implement verification testbenches using industry-standard verification methodologies (e.g., UVM, SystemVerilog, VHDL).
• Simulation and Debugging: Perform simulations, analyze results, and debug issues related to timing, protocol errors, and other design anomalies in SerDes blocks. Debug test failures to determine the root cause; work with RTL and firmware engineers to resolve design defects and correct any test issues.
• Performance Evaluation: Evaluate and validate performance characteristics of SerDes systems including jitter, bit error rates (BER), signal integrity, eye diagrams, and other key metrics.
• Protocol Compliance Testing: Verify adherence to relevant SerDes protocols such as UCIe , PCIe, Ethernet, USB, DDR, DisplayPort, or custom protocols.
• Automated Testing: Develop automated regression tests to ensure the robustness and stability of the SerDes design over multiple versions and iterations.
• Collaboration: Work closely with the design, hardware, and software teams to troubleshoot issues, implement fixes, and verify design changes.
• Documentation: Create detailed reports and documentation on verification results, test scenarios, and issues found during testing.
• Continuous Improvement: Provide feedback for design and verification process improvements and contribute to innovation in verification strategies and methodologies.

PREFERRED EXPERIENCE:

• Experience in SerDes verification or high-speed communication verification.
• Strong hands‑on experience with verification methodologies such as UVM, SystemVerilog, or other simulation‑based verification tools.
• Knowledge of high-speed serial protocols such as UCIe, PCIe, Ethernet, USB, DDR, or custom protocols.
• Experience in analyzing and interpreting signal integrity issues, jitter, BER, and eye diagrams.
• Solid understanding of SerDes architectures, link training, and equalization.
• Strong debugging skills, with the ability to work across multiple domains (timing, protocol, performance).
• Familiarity with hardware description languages (HDL) like VHDL or Verilog.
• Strong analytical, problem‑solving, and communication skills.
• Experience with DDR protocol (e.g., DDR3, DDR4, DDR5) for memory interface verification.
• Understanding of UCIe protocol and its role in chiplet‑to‑chiplet communication.
• Experience with Python, Perl, or similar scripting languages for automation.
• Exposure to high-speed memory interface design and verification, including DDR controller IP verification.
• Ability to work in a fast‑paced environment and manage multiple verification tasks.

ACADEMIC CREDENTIALS:

Bachelors or Masters degree in Computer Engineering/Electrical Engineering

LOCATION:

Singapore