Senior / Staff SerDes Digital Design

Uni Connect; Singapore; On-site; SGD 80,000 - 120,000; Full time

Job summary

A technology solutions company in Singapore is seeking a qualified engineer with extensive ASIC design experience. The ideal candidate will have a Bachelor's degree in a relevant field and more than 6 years of ASIC design expertise. Responsibilities include participating in product specifications, performing RTL coding, and collaborating with teams for debugging. Strong communication skills in English are essential, with Chinese language skills preferred. This role offers opportunities to work on innovative memory interfaces.

Qualifications

• More than 6 years (staff engineer) and 10 years (senior staff engineer) of ASIC design experience, familiar with ASIC development process.
• Good Verilog HDL coding skills and EDA tools such as synthesis and timing analysis.
• Familiarity with high-speed interfaces such as DDR, SerDes, PCIe preferred.

Responsibilities

• Participate in high-level product specifications, microarchitecture, and implementation of high-speed memory interfaces.
• Perform RTL coding, LINT checking and sanity testing on implemented designs.
• Work with the verification team for lab debugging.
• Work with the software team and/or customers to solve problems and debug.

Skills

Verilog HDL coding

Problem-solving

Organizational skills

Communication skills

Familiarity with EDA tools

Education

Bachelor's degree in communications, electronic engineering, or computer engineering

Master's degree

Job description

Singapore, Singapore | Posted on 10/04/2024

• Participate in high-level product specifications, microarchitecture and implementation of high-speed memory interfaces
  
• Perform RTL coding, LINT checking and sanity testing on implemented designs
  
• Work with the verification team for lab debugging
  
• Work with the software team and/or customers to solve problems, debug and tune system performance
  

Requirements

• Bachelor's degree in communications, electronic engineering or computer engineering, master’s degree preferred
  
• More than 6 years (staff engineer) and 10 years (senior staff engineer) of ASIC design experience, familiar with ASIC development process
  
• Good Verilog HDL coding skills and EDA tools such as synthesis and timing analysis
  
• Familiarity with high-speed interfaces such as DDR, SerDes, PCIe is preferred
  
• Ability to solve customer problems and deliver results in a timely manner
  
• Strong organizational and communication skills where English is a must and Chinese is preferred