Senior / Staff Physical Verification Engineer

dadaconsultants pte. ltd.; Singapore; On-site; SGD 90,000 - 150,000; Full time

Job summary

dadaconsultants pte. ltd. seeks a Senior/Staff Physical Verification Engineer to own PV signoff for advanced-node ASIC/SoC at the block and full-chip levels.

You will collaborate with Place & Route to resolve layout issues and drive tape-out milestones in a fast-paced, high-impact environment. You will harness Calibre and scripting (Python, Perl, Tcl, Make) to automate flows and improve efficiency, contributing to method development and back-end signoff processes.

Qualifications

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or closely related field.
• Minimum 5 years of PV experience on advanced nodes.
• Experience with Calibre or equivalent physical verification tools.
• Familiarity with Python, Perl, Tcl, or Make for automation (bonus).

Responsibilities

• Execute PV signoff for advanced-node ASIC/SoC designs (DRC, LVS, ERC, ESD, PERC/Reliability, density/fill, tape-out checks).
• Manage PV runs end-to-end, including hierarchical/flat modes and resource optimisation.
• Collaborate with Place & Route to fix full-chip layout issues.
• Support PV flow from netlist to GDSII delivery ensuring process compliance.
• Develop automation to streamline tape-out workflows and improve efficiency.
• Contribute to PV methodology and scripting libraries using Perl and Tcl.
• Align signoff criteria with circuit design and backend teams to drive timely tape-outs.

Skills

PV Signoff ownership

Team collaboration

Education

Bachelor's or Master's degree in Electrical/Computer Engineering

Tools

Calibre

Python

Perl

Tcl

Make

Job description

Senior / Staff Physical Verification Engineer

About the Role

Our client is a globally operating technology company specialising in high-performance computing infrastructure and AI cloud services, with a diversified energy portfolio spanning multiple continents and a strong focus on next-generation chip design. They are headquartered in Singapore and are at the forefront of developing industry-grade ASIC solutions on leading-edge process nodes. This role offers a unique opportunity to take full ownership of physical verification signoff at both block and full-chip levels, working at the intersection of circuit design and backend implementation in a fast-paced, high-impact environment.

Key Responsibilities

• Execute comprehensive Physical Verification (PV) signoff for advanced-node ASIC/SoC designs, covering DRC, LVS, ERC, ANT, ESD, PERC/Reliability, density/fill, and all foundry-mandated tape-out checks
• Monitor and manage PV runs end-to-end, including hierarchical and flat execution modes, runtime and resource optimisation, result tracking, issue prioritisation, and milestone-driven closure toward tape-out
• Collaborate closely with Place & Route engineers to identify and resolve full-chip layout integration issues
• Support the complete physical design flow from netlist through to GDSII delivery, ensuring design quality and process compliance at every stage
• Develop and implement automation solutions to streamline tape-out workflows and improve team efficiency
• Contribute to internal physical design methodology, scripting libraries, and flow automation using Perl and Tcl
• Partner with circuit design and backend teams to align on signoff criteria and drive timely tape-out execution

Requirements

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a closely related discipline
• Minimum 5 years of hands-on physical verification experience on advanced process nodes, with experience at N4 or below strongly preferred (experience specifically on TSMC nodes is a bonus)
• Demonstrated proficiency with Calibre or equivalent industry-standard physical verification tools
• Solid understanding of the end-to-end IC design flow, from front-end design through backend implementation and full signoff
• Prior tape-out experience is required; familiarity with Python, Perl, Tcl, or Make scripting for flow automation (is a bonus)