Senior Research Fellow [BS-PDN]

National University of Singapore; Singapore; On-site; SGD 150,000 - 180,000; Full time

Job summary

National University of Singapore (NUS) seeks a Senior Research Fellow to lead BS-PDN research and develop optimization methods for advanced packaging, including 3DIC and chiplet-based architectures. The role involves modeling, data-driven approaches, and close industry-academic collaboration.

The successful candidate will mentor students and junior researchers, drive project roadmaps, and contribute to proposals, publications, and IP activities within the Electrical and Computer Engineering

Qualifications

• PhD in a relevant engineering or science field is preferred, or equivalent experience.
• Experience in microelectronic research, metrology, electrical testing, and data analysis is advantageous.
• Expanded project management experience with ownership of deliverables.
• Strong communication skills for collaboration and dissemination.

Responsibilities

• Lead BS-PDN research and System-Technology Co-Optimization for advanced logic, chiplet-based, and 3DIC systems.
• Define strategic R&D roadmap and drive BS-PDN and advanced packaging initiatives; develop multi-physics workflows.
• Mentor junior researchers and manage project resources, budgets, and industry collaborations.
• Publish findings in journals and conferences; contribute to invention disclosures and tech transfer.

Skills

Data analysis

Communication

Independent work

Leadership

Education

PhD in Electrical/Electronic/Mechanical/Chemical Engineering or related field

Experience in microelectronic research and data analysis

Job description

Job Title: Senior Research Fellow [BS-PDN]

University-Level Unit: College of Design and Engineering

Faculty/Department-Level Unit: Electrical and Computer Engineering

Employee Category: Research Staff

Location_ONB: Kent Ridge Campus

Posting Start Date: 24/07/2026

Job Description

The ECE Department at NUS is seeking a Senior Research Fellow to support advanced research and provide technical leadership in Backside Power Delivery Networks (BS-PDN) and advanced semiconductor packaging. The successful candidate will play a dual role: spearheading the development of on developing and integrating modeling, co-design, and data-driven optimization methodologies for BS-PDN-enabled systems, including 3DIC and chiplet-based architectures. This position offers an exciting opportunity to work at the forefront of semiconductor technology, with close collaboration across industry partners and academic researchers.

Responsibilities will involve:

1. 1. Research & Development
   • Lead System-Technology Co-Optimization (STCO) research on BS-PDN for advanced logic, chiplet-based, and 3DIC systems, following UCIe standard.
   • Define and drive the strategic research roadmap for BS-PDN and advanced packaging initiatives
   • Develop and integrate simulation-driven workflows combining electrical, thermal, and mechanical analyses for BS-PDN-enabled systems.
   • Develop novel design methodologies, modeling approaches, and optimization techniques for BS-PDN, addressing power integrity, thermal management, and chip–package interaction challenges.
   • Manage the generation, preprocessing, and analysis of large-scale multi-physics simulation and design datasets related to BS-PDN integration.
   • Drive optimization of BS-PDN layouts, backside vias, redistribution layers, and embedded passives to meet real-world performance and manufacturability requirements.
   • Validate predictive models and design outcomes against reference simulations and experimental test vehicles
2. 2. Leadership & Project Management
   • Lead, supervise, and mentor junior researchers, postdoctoral fellows, and graduate students, fostering a culture of scientific excellence and collaborative innovation.
   • Actively contribute to or lead the drafting of research proposals for competitive funding and manage project resources, budgets, and technical allocations effectively.
   • Serve as a key technical interface with industry partners (foundries, OSATs, EDA vendors) to align research objectives with industry needs.
   • Contribute to joint development activities and technology transfer efforts related to BS-PDN adoption.
3. 3. Data Analysis & Reporting
   • Take ownership of technical deliverables and research milestones, ensuring timely execution within project schedules.
   • Prepare technical reports, peer-reviewed publications, and presentations for academic, industrial, and consortium stakeholders.
4. 5. Innovation & Intellectual Property
   • Contribute to invention disclosures, patent filings, and technology commercialization activities.
   • Publish research outcomes in high-impact journals and present at leading semiconductor and packaging conferences.

Qualifications

• Ph.D. or equivalent degree in Electrical, Electronics, Mechanical, Chemical Engineering, Physics, Material Science or its equivalent from a reputable University/Institute is preferred, or equivalent related experience.
• Candidate with experience in microelectronic research, characterisation, metrology and electrical testing, and strong in data analysis will have advantage.
• Expanded Project Management: Acting as the primary technical interface and taking full ownership of deliverables
• Proficiency in data analysis and interpretation using statistical tools and software packages.
• Excellent communication skills and the ability to work effectively in a collaborative research environment.
• Motivated and possesses effective communication skills including writing and presenting.
• Ability to work independently and collaborate within a diverse team.
• Open to Fixed Term Contract.