Research Fellow (IC Designer)

National University of Singapore; Singapore; On-site; SGD 67,000 - 112,000; Full time

Job summary

National University of Singapore invites applications for a Research Fellow (IC Designer) in the SHINE Centre 2.0 within the Department of Electrical and Computer Engineering at Kent Ridge Campus. The role focuses on modeling, design exploration, and test-chip demonstrations for predictive power management.

The appointment is initially for 1 year with potential extension. Salary will be commensurate with qualifications and experience.

Qualifications

• PhD in Electrical Engineering or related field.
• Knowledge of circuit architectures and transistor-level design.
• Familiarity with silicon chip design and EDA tools.
• Ability to work independently and in a team.
• Good communication and interpersonal skills.
• Open to fixed term contract.

Responsibilities

• Modeling and verification of physical, thermal and circuit-to-system behavior.
• High-level modeling for predictive power management.
• Developing voltage-aware models and test-chip demonstrations.
• Integrating voltage/temperature-aware circuits and models.
• Runtime adaptation for event detection with test-chip demonstrations.
• Authoring research papers and presenting findings at conferences.
• Provide technical guidance to PhD and Master’s students.

Skills

Circuit architectures

Transistor-level design

Silicon chip design

EDA tools

Independent and collaborative work

Communication skills

Education

PhD in Electrical Engineering or related

Tools

EDA tools

Job description

Job Title: Research Fellow (IC Designer)
University-Level Unit: College of Design and Engineering
Faculty/Department-Level Unit: Electrical and Computer Engineering
Employee Category: Research Staff
Location_ONB: Kent Ridge Campus
Posting Start Date: 22/06/2026

Job Description

We are looking for a Research Fellow for the (SHINE) Centre 2.0 co-led by Professor Massimo Alioto, at the Department of Electrical and Computer Engineering, National University of Singapore (NUS).

The Selected Candidate Is Expected To Work On

• physical, thermal and circuit-to-system modeling, design exploration, architecture and validation/testing framework
• high-level exploration and modeling for predictive power management
• predictive power management from circuits to voltage-aware model optimization and test chip demonstration
• predictive power management from circuits to voltage and temperature-aware model optimization and test chip demonstration
• predictive power management runtime adaptation for accurate event detection with test chip demonstration
• full integration of voltage/temperature-aware circuits, models and runtime adaptation for accurate event detection
• authoring high-quality research papers for leading conferences and journals and presenting findings at international conferences.
• managing technical milestones for the project and providing technical guidance to PhD and master’s students within the group.

The appointment can commence immediately with a 1-year contract, with prospect of extension. Salary will be commensurate with qualifications and experience.

Qualifications

• A PhD degree in either Electrical Engineering or strictly related (e.g., Computer, Electronics, Communication, or Information Engineering).
• Knowledge on circuit architectures, transistor-level design.
• Knowledge on silicon chip design, EDA tools.
• Ability to work independently and collaboratively in a team environment.
• Good communication and interpersonal skills.
• Open to fixed term contract.

Req ID: 33444