Senior /Lead Research Engineer (FOWLP/2.5D/3D package integration) (HI), IME

A*STAR International; Singapore; Sur place; SGD 120 000 - 180 000; Plein temps

Résumé du poste

The Institute of Microelectronics (IME) invites a Senior/Lead Research Engineer to advance cutting-edge packaging technology, including fan-out, 2.5D interposers, and 3D stacking for heterogeneous integration. You will collaborate with design, process, and external partners to define design rules, develop test vehicles, and drive qualification through pilot to production.

Ideal candidates hold a Bachelor's or Master's in a relevant field and have 5–10 years in semiconductor backend integration,

Qualifications

• Semiconductor experience with Cu backend integration.
• Expertise in flip-chip, FOWLP, 2.5D/3D, TSVs, and fusion/hybrid bonding.
• Experience with design rules, PDKs, and process integration.
• Strong communication and ability to work in diverse teams.

Responsabilités

• Develop packaging platforms: fan-out, 2.5D interposer, 3D stacking.
• Lead internal/external projects with new materials and tests.
• Coordinate with design, process, and yield teams; manage schedules.
• Mentor students and engage with partners and universities.

Connaissances

Cu backend integration

2.5D packaging

FOWLP

3D stacking

design rules & PDK

DOE & SPC

cross-functional teamwork

leadership/mentoring

Formation

Bachelor's or Master's in related field

Outils

JMP

Minitab

Description du poste

Job Title: Senior /Lead Research Engineer (FOWLP/2.5D/3D package integration) (HI), IME

Job Description

The advanced Packaging Program at the Institute of Microelectronics (IME) is seeking a passionate and skilled Scientist or Senior Scientist to join our team. This role is pivotal in advancing the state-of-the-art advanced packaging platform technologies, such as 2.5D/3D IC and Co-packaged optics. Development of critical modules includes fine pitch multi-layer redistribution layers (RDL), micro bumping, Temporary bonding and debonding process flow, flip chip thermal compression bonding, chip-to-wafer and wafer-to-wafer fusion/hybrid bonding capabilities, developing fan-out wafer level packaging, 2.5D interposer, and 3D chip stacking process integration flows for Heterogeneous Integration of chiplets.

The position provides an exciting opportunity to contribute to groundbreaking technologies and collaborate with a dynamic team of researchers and external ecosystem stakeholders

Key Responsibilities:

Develop advanced packaging technology platforms (fan-out packaging, 2.5D interposer and 3D stacking) capabilities and novel process integration approaches for heterogeneous chiplets integration.

Work with design and process module teams to establish design rules and PDK for advanced packaging technologies.

Lead capability development projects for internal and external industry projects involving new materials, advanced process integration approaches, and new test vehicle designs with minimum manageable risks.

Engage and manage internal and external stakeholders for project activities execution and provide timely updates on schedule and deliverables.

Act as a subject matter expert (SME) for both internal and external stakeholders, providing guidance and expertise.

Collaborate with cross-functional teams such as design, Unit process team, yield improvement, and external partners, including materials, equipment, customers and universities, to identify technology gaps, define technology roadmap and drive the development.

Inspire and mentor students in semiconductor technology, contributing to workforce development in advanced packaging.

Customer/partner engagement: ability to present technical content to customers and senior stakeholders; drive joint development (JDP/NRE).

Mentoring junior engineers, influencing without authority, and ownership of module roadmaps.

Should be able to work hands-on in the cleanroom and learning new processes and metrology equipments

Job Requirements

Bachelor's or Master's in Materials Science & Engineering, Mechanical, Chemical, Electronics/ Electrical & Computer Engineering, Physics, Chemistry or a closely related field.

5-10 years of experience in semiconductor experience with expertise in Cu backend integration and exposure to advanced packaging technologies (flip-chip, FOWLP, 2.5D/3D, TSV, hybrid/fusion bonding).

Broad hands-on knowledge of one or more unit processes—such as lithography, etch (damascene, TSV via-last/middle); deposition (ALD/CVD/PVD, including high-AR barrier and seed layers); electroplating and alternative via-fill materials, CMP for hybrid bonding; fusion/hybrid bonding; wafer thinning; and dicing—is preferred.

Proven ability to work effectively in a diverse, matrixed environment and collaborate with cross-functional departments.

Strong analytical/problem-solving skills (Ishikawa, Seven Basic Quality Tools, brainstorming) and proficiency with DOE and SPC (JMP/Minitab).

NPI to HVM ramp experience: process window definition, control plans, and yield/cost improvement through pilot to high-volume manufacturing (foundry/OSAT).

Reliability & standards: working knowledge of JEDEC/IPC/JESD (e.g., HTS, TC, HAST, BLR, EM), and failure analysis flows (X-ray, CSAM, FIB/SEM-EDX).

Excellent written and verbal communication abilities.

Demonstrated ability to manage multiple projects and priorities in a research and translational environment.

Able to work effectively with multi-ethnic, multicultural teams and to build inclusive, high-performing teams.

What We Offer:

The opportunity to work on cutting-edge research projects in advanced packaging and heterogeneous integration.

A collaborative & interdisciplinary work environment and access to state-of-the-art facilities and resources.

File intellectual property (IP) promptly for new research findings.

Publish research in peer-reviewed journals and present findings at international conferences.

Researchers have access to advanced laboratories and characterisation equipment, fostering innovation and enabling the development of groundbreaking technologies. The institute encourages interdisciplinary collaboration and offers opportunities for professional growth and development.

Bachelor's or Master's in Materials Science & Engineering, Mechanical, Chemical, Electronics/ Electrical & Computer Engineering, Physics, Chemistry or a closely related field.

5-10 years of experience in semiconductor experience with expertise in Cu backend integration and exposure to advanced packaging technologies (flip-chip, FOWLP, 2.5D/3D, TSV, hybrid/fusion bonding).

Broad hands-on knowledge of one or more unit processes—such as lithography, etch (damascene, TSV via-last/middle); deposition (ALD/CVD/PVD, including high-AR barrier and seed layers); electroplating and alternative via-fill materials, CMP for hybrid bonding; fusion/hybrid bonding; wafer thinning; and dicing—is preferred.

Proven ability to work effectively in a diverse, matrixed environment and collaborate with cross-functional departments.

Strong analytical/problem-solving skills (Ishikawa, Seven Basic Quality Tools, brainstorming) and proficiency with DOE and SPC (JMP/Minitab).

NPI to HVM ramp experience: process window definition, control plans, and yield/cost improvement through pilot to high-volume manufacturing (foundry/OSAT).

Reliability & standards: working knowledge of JEDEC/IPC/JESD (e.g., HTS, TC, HAST, BLR, EM), and failure analysis flows (X-ray, CSAM, FIB/SEM-EDX).

Excellent written and verbal communication abilities.

Demonstrated ability to manage multiple projects and priorities in a research and translational environment.

Able to work effectively with multi-ethnic, multicultural teams and to build inclusive, high-performing teams.

What We Offer:

The opportunity to work on cutting-edge research projects in advanced packaging and heterogeneous integration.

A collaborative & interdisciplinary work environment and access to state-of-the-art facilities and resources.

File intellectual property (IP) promptly for new research findings.

Publish research in peer-reviewed journals and present findings at international conferences.

Researchers have access to advanced laboratories and characterisation equipment, fostering innovation and enabling the development of groundbreaking technologies. The institute encourages interdisciplinary collaboration and offers opportunities for professional growth and development.

The above eligibility criteria are not exhaustive. A*STAR may include additional selection criteria based on its prevailing recruitment policies. These policies may be amended from time to time without notice. We regret that only shortlisted candidates will be notified.