Senior Physical Design Lead for High-Speed Transceivers

Astera Labs; Singapore; On-site; SGD 120,000 - 180,000; Full time

Job summary

Astera Labs seeks a Senior Physical Design Engineer to join a high-performance design team. You will perform block-level and top-level physical implementation for transceiver IPs targeting advanced nodes, collaborating with RTL/STA teams to meet timing, area, and power goals.

Responsibilities include EM/IR, congestion analysis, clock skew optimization, RC extraction-aware routing, and ECO/tapeout support. Proficiency with ICC2, Innovus, Calibre, Voltus and scripting is required.

Qualifications

• Bachelor’s or Master’s degree in Electrical Engineering, Electronics Engineering, or a related field.
• 5+ years of experience in physical design, preferably with advanced technology nodes.
• Strong scripting skills for automation and productivity.
• We actively encourage diverse candidates to apply.

Responsibilities

• Perform block-level and top-level physical implementation including floorplanning, placement, CTS, routing, and physical verification for high-speed designs in advanced technology nodes.
• Collaborate with RTL and STA teams to ensure clean handoffs and support timing, area, and power convergence.
• Apply advanced physical design techniques to support multiple voltage and frequency domains, hierarchical design, and physical-aware synthesis.
• Work on key physical design areas including EM/IR analysis and power grid optimization, congestion analysis, clock skew optimization, RC extraction-aware placement and routing.
• Integrate IPs and top-level blocks with attention to physical interfaces, constraints, and timing alignment; support floorplan development and chip partitioning.
• Perform ECO implementation and assist with tapeout signoff activities.
• Ensure DRC, LVS, ANT, CELL, and ERC clean databases using industry-standard physical verification tools.
• Use tools like ICC2, Innovus, Calibre, and Voltus for implementation and signoff.
• Develop and maintain automation scripts in Tcl, Python, or Perl to improve physical design flows and productivity.

Skills

Floorplanning

Placement

CTS

Routing

IR drop mitigation

DRC LVS

Signoff checks

Timing closure

Scripting

IP integration

Education

Bachelor’s or Master’s degree in Electrical Engineering, Electronics Engineering, or related field

Tools

ICC2

Innovus

Calibre

Voltus

Job description

Astera Labs seeks a Senior Physical Design Engineer to join a high-performance design team. You will perform block-level and top-level physical implementation for transceiver IPs targeting advanced nodes, collaborating with RTL/STA teams to meet timing, area, and power goals.

Responsibilities include EM/IR, congestion analysis, clock skew optimization, RC extraction-aware routing, and ECO/tapeout support. Proficiency with ICC2, Innovus, Calibre, Voltus and scripting is required.