Senior Physical Design Engineer — High‑Speed Transceivers

Astera Labs; Singapore; Presencial; SGD 140 000 - 190 000; Tempo integral

Resumo da oferta

Astera Labs in Singapore is seeking a Senior Physical Design Engineer to join a high-performance team working on next-generation transceiver IPs for 3nm nodes. You will own block-level and top-level physical implementation, including floorplanning, placement, CTS, routing and physical verification for high-speed designs.

Collaborate with RTL and STA teams to ensure clean handoffs, support timing, area and power convergence, and apply physical design techniques across multiple domains.

Qualificações

• Bachelor’s or Master’s degree in Electrical Engineering or related field.
• 5-10 years of experience in physical design, preferably on advanced nodes.
• Extensive experience with floorplanning, placement, CTS, routing, and IR drop mitigation.
• Experience with DRC/LVS/ANT/ERC signoff and debugging in signoff tools.
• Timing closure support in collaboration with STA teams.
• Hands-on use of ICC2, Innovus, Calibre, and Voltus for implementation and signoff.
• Experience integrating high-speed IPs/SerDes into SoC or chiplet environments.

Responsabilidades

• Perform block-level and top-level physical implementation including floorplanning, placement, CTS, routing, and physical verification.
• Collaborate with RTL and STA teams to ensure clean handoffs and support timing, area, and power convergence.
• Apply advanced physical design techniques to support multiple voltage/frequency domains and hierarchical design.
• Work on EM/IR analysis, power grid optimization, congestion mitigation, and clock skew improvements.
• Integrate IPs and top-level blocks with attention to interfaces, constraints, and timing alignment.
• Assist floorplan development and chip partitioning for high-speed transceiver designs.
• Perform ECO implementation and support tapeout signoff; ensure clean databases with PV tools.
• Develop automation scripts in Tcl/Python/Perl to improve design flows.

Conhecimentos

Floorplanning

Placement

CTS

IR drop

Power integrity

Signoff

Scripting

Formação académica

Bachelor’s or Master’s degree in Electrical Engineering

Ferramentas

ICC2

Innovus

Calibre

Voltus

Descrição da oferta de emprego

Astera Labs in Singapore is seeking a Senior Physical Design Engineer to join a high-performance team working on next-generation transceiver IPs for 3nm nodes. You will own block-level and top-level physical implementation, including floorplanning, placement, CTS, routing and physical verification for high-speed designs.

Collaborate with RTL and STA teams to ensure clean handoffs, support timing, area and power convergence, and apply physical design techniques across multiple domains.