Senior Physical Design Engineer - High-Speed IP & Tapeout

Astera Labs; Singapore; On-site; SGD 120,000 - 190,000; Full time

Job summary

Astera Labs seeks a Senior Physical Design Engineer to join a high-performance team working on transceiver IPs for TSMC 3nm and beyond. You will drive block/top-level implementation, floorplanning, CTS, routing, and signoff in advanced nodes.

You will collaborate with RTL/STA teams to optimize timing, area, and power, apply multi-domain design techniques, and develop automation scripts to improve flows.

Qualifications

• Bachelor’s or Master’s degree in Electrical/Electronics Engineering or related field.
• 5+ years of physical design experience, preferably on advanced nodes.
• Experience with floorplanning, placement, CTS, routing and IR drop mitigation.
• Proficient with signoff checks (DRC/LVS/ANT/ERC) and timing closure.

Responsibilities

• Perform block-level and top-level physical implementation including floorplanning, placement, CTS, routing, and verification.
• Collaborate with RTL/STA teams to ensure timing, area, and power convergence.
• Apply physical design techniques for multiple voltage/frequency domains and hierarchical design.
• Address EM/IR, congestion, clock skew, and RC extraction-aware placement and routing.
• Integrate IPs and top-level blocks with cognizant interfaces and timing alignment.
• Support floorplan development and chip partitioning for high-speed transceivers.
• Execute ECO implementation and assist tapeout signoff activities.

Skills

Physical design

Floorplanning

Timing closure

Power/IR drop

Scripting (Python/Tcl)

Education

Bachelor's or Master's in Electrical Engineering

Tools

Synopsys ICC2

Cadence Innovus

Calibre

Voltus

Job description

Astera Labs seeks a Senior Physical Design Engineer to join a high-performance team working on transceiver IPs for TSMC 3nm and beyond. You will drive block/top-level implementation, floorplanning, CTS, routing, and signoff in advanced nodes.

You will collaborate with RTL/STA teams to optimize timing, area, and power, apply multi-domain design techniques, and develop automation scripts to improve flows.