Senior Physical Design Engineer: High-Speed IP & Tapeout

asteralabs; Singapore; On-site; SGD 120,000 - 180,000; Full time

Job summary

Astera Labs in Singapore is seeking a Senior Physical Design Engineer to drive block- and top-level physical implementation for next-gen transceiver IPs on advanced nodes. You will collaborate with RTL and STA teams to ensure timing, area, and power convergence while handling floorplanning, CTS, routing, and physical verification.

The role requires 5+ years in physical design, strong scripting skills, and hands-on use of ICC2, Innovus, Calibre, and Voltus.

Qualifications

• Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering, or related field.
• 5+ years of experience in physical design, preferably with advanced technology nodes.
• Experience with floorplanning, placement, CTS, routing, and IR drop mitigation.

Responsibilities

• Perform block-level and top-level physical implementation including floorplanning, placement, CTS, routing, and physical verification.
• Collaborate with RTL and STA teams to ensure clean handoffs and support timing, area, and power convergence.
• Apply advanced physical design techniques to support multiple voltage and frequency domains, hierarchical design, and physical-aware synthesis.
• Work on EM/IR analysis, power grid optimization, congestion analysis and mitigation, clock skew optimization.
• Integrate IPs and top-level blocks with attention to physical interfaces, constraints, and timing alignment.
• Support floorplan development and chip partitioning for high-speed transceiver designs.
• Perform ECO implementation and assist with tapeout signoff activities.

Skills

Floorplanning

Placement

CTS

Routing

IR drop mitigation

Timing closure

Scripting

Education

Bachelor's or Master's in Electrical/ Electronics Engineering

Tools

Synopsys ICC2

Cadence Innovus

Calibre

Voltus

Job description

Astera Labs in Singapore is seeking a Senior Physical Design Engineer to drive block- and top-level physical implementation for next-gen transceiver IPs on advanced nodes. You will collaborate with RTL and STA teams to ensure timing, area, and power convergence while handling floorplanning, CTS, routing, and physical verification.

The role requires 5+ years in physical design, strong scripting skills, and hands-on use of ICC2, Innovus, Calibre, and Voltus.