Senior Physical Design Engineer for 3nm Transceivers

Astera Labs; Singapore; On-site; SGD 120,000 - 180,000; Full time

Job summary

Astera Labs, a NASDAQ-listed company, seeks a Senior Physical Design Engineer to join its high-performance team for next-generation transceiver IPs targeting TSMC 3nm and beyond. The role focuses on physical implementation, floorplanning, CTS, routing, and signoff across advanced technology nodes.

The ideal candidate has 5+ years in physical design, hands-on experience with industry tools (ICC2, Innovus, Calibre, Voltus), and scripting ability to automate flows.

Qualifications

• Bachelor’s or Master’s degree in Electrical Engineering, Electronics Engineering, or related field.
• 5+ years of experience in physical design, preferably with advanced technology nodes.
• Strong experience with floorplanning, placement, CTS, routing, and IR drop mitigation.
• Signoff checks such as DRC, LVS, ANT, and ERC, with debugging.
• Timing closure support in collaboration with STA teams.
• Hands-on use of tools such as Synopsys ICC2, Cadence Innovus, Calibre, and Voltus.
• Experience integrating high-speed IPs such as SerDes or PHYs into SoC or chiplet-based environments.
• Experience working on high-frequency datapath and DSP-related designs.
• Solid scripting skills for automation and productivity enhancement.

Responsibilities

• Perform block-level and top-level physical implementation including floorplanning, placement, CTS, routing, and physical verification.
• Collaborate with RTL and STA teams to ensure clean handoffs and support timing, area, and power convergence.
• Apply advanced physical design techniques to support multiple voltage and frequency domains, hierarchical design, and physical-aware synthesis.
• Work on EM/IR analysis, power grid optimization, congestion analysis, and clock skew optimization.
• Integrate IPs and top-level blocks with attention to physical interfaces, constraints, and timing alignment.
• Support floorplan development and chip partitioning for high-speed transceiver designs.
• Perform ECO implementation and assist with tapeout signoff activities.
• Ensure DRC, LVS, ANT, CELL, and ERC clean databases using industry-standard physical verification tools.
• Use tools like ICC2, Innovus, Voltus, RedHawk, and Calibre for implementation and signoff.
• Develop and maintain automation scripts in Tcl, Python, or Perl.

Skills

Floorplanning

Placement

CTS

Routing

IR drop mitigation

Timing closure

Automation scripting

Education

Bachelor’s or Master’s degree in Electrical Engineering

Tools

Synopsys ICC2

Cadence Innovus

Calibre

Voltus

Job description

Astera Labs, a NASDAQ-listed company, seeks a Senior Physical Design Engineer to join its high-performance team for next-generation transceiver IPs targeting TSMC 3nm and beyond. The role focuses on physical implementation, floorplanning, CTS, routing, and signoff across advanced technology nodes.

The ideal candidate has 5+ years in physical design, hands-on experience with industry tools (ICC2, Innovus, Calibre, Voltus), and scripting ability to automate flows.