Senior Physical Design Engineer - High-Speed IP & Tapeout

ASTERA LABS SINGAPORE PRIVATE LIMITED

Singapore

On-site

SGD 120,000 - 170,000

Full time

14 days+
Application generator

Turn this role into an interview — a resume and cover letter built around what this employer wants.

Get past ATS filters

Job summary

Astera Labs Singapore is seeking a Senior Physical Design Engineer to join our high-performance team working on transceiver IPs for 3nm tech, focusing on floorplanning, CTS, routing, and tapeout readiness.

You will collaborate with RTL/STA teams, optimize IR drop, power, and clocking, and use ICC2, Innovus, Calibre, Voltus while developing automation scripts. This role requires 5+ years in physical design.

Qualifications

  • Bachelor's or Master's degree in Electrical Engineering or related field.
  • 5+ years of experience in physical design, preferably with advanced technology nodes.
  • Hands-on with floorplanning, placement, CTS, routing, and signoff checks (DRC/LVS/ANT/ERC).

Responsibilities

  • Perform block-level/top-level physical implementation (floorplanning, placement, CTS, routing, verification).
  • Collaborate with RTL/STA teams to support timing, area, and power convergence.
  • Apply advanced techniques for multi-volt/frequency domains and physical-aware synthesis.
  • Work on EM/IR, power grid optimization, congestion analysis, clock skew, RC extraction-aware placement.
  • Integrate IPs/blocks with proper interfaces and timing alignment; support floorplan and tapeout signoff.
  • Develop automation scripts in Tcl/Python/Perl to improve flows.
  • Ensure DRC, LVS, ANT, ERC clean databases with industry-standard tools.

Skills

Scripting
Cross-functional teamwork
Problem solving

Education

Bachelor or Master in Electrical Engineering or related field

Tools

Synopsys ICC2
Cadence Innovus
Calibre
Voltus

Job description

Astera Labs Singapore is seeking a Senior Physical Design Engineer to join our high-performance team working on transceiver IPs for 3nm tech, focusing on floorplanning, CTS, routing, and tapeout readiness.

You will collaborate with RTL/STA teams, optimize IR drop, power, and clocking, and use ICC2, Innovus, Calibre, Voltus while developing automation scripts. This role requires 5+ years in physical design.

Get your free, confidential resume review.

or drag and drop your file here.

Similar jobs

Similar jobs worth comparing

Senior Physical Design Engineer: High-Speed IP & Tapeout
Senior Physical Design Engineer: High-Speed IP & Tapeout

asteralabs • Singapore

On-site
SGD 120,000 - 180,000
Senior Physical Design Engineer - High-Speed IP & Tapeout
Senior Physical Design Engineer - High-Speed IP & Tapeout

Astera Labs • Singapore

On-site
SGD 120,000 - 190,000
Senior Physical Design Engineer — High‑Speed Transceivers
Senior Physical Design Engineer — High‑Speed Transceivers

Astera Labs • Singapore

On-site
SGD 140,000 - 190,000
Senior Physical Design Lead for High-Speed Transceivers
Senior Physical Design Lead for High-Speed Transceivers

Astera Labs • Singapore

On-site
SGD 120,000 - 180,000
Senior Physical Design Engineer for 3nm Transceivers
Senior Physical Design Engineer for 3nm Transceivers

Astera Labs • Singapore

On-site
SGD 120,000 - 180,000
Principal Physical Design Engineer - High-Speed SoC
Principal Physical Design Engineer - High-Speed SoC

asteralabs • Singapore

On-site
SGD 120,000 - 190,000
Senior Engineer - Physical Design
Senior Engineer - Physical Design

ASTERA LABS SINGAPORE PRIVATE LIMITED • Singapore

On-site
SGD 120,000 - 170,000
Principal Engineer PD New Singapore, Singapore
Principal Engineer PD New Singapore, Singapore

Astera Labs • Singapore

On-site
SGD 120,000 - 180,000
Teach Lead Physical Design Engineer
Teach Lead Physical Design Engineer

asteralabs • Singapore

On-site
SGD 120,000 - 180,000
Principal Physical Design Engineer
Principal Physical Design Engineer

Astera Labs • Singapore

On-site
SGD 140,000 - 190,000