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Astera Labs Singapore is seeking a Senior Physical Design Engineer to join our high-performance team working on transceiver IPs for 3nm tech, focusing on floorplanning, CTS, routing, and tapeout readiness.
You will collaborate with RTL/STA teams, optimize IR drop, power, and clocking, and use ICC2, Innovus, Calibre, Voltus while developing automation scripts. This role requires 5+ years in physical design.
Astera Labs Singapore is seeking a Senior Physical Design Engineer to join our high-performance team working on transceiver IPs for 3nm tech, focusing on floorplanning, CTS, routing, and tapeout readiness.
You will collaborate with RTL/STA teams, optimize IR drop, power, and clocking, and use ICC2, Innovus, Calibre, Voltus while developing automation scripts. This role requires 5+ years in physical design.