junior/senior layout engineer

ASTRAWAVE TECHNOLOGY; Singapore; On-site; SGD 90,000 - 160,000; Full time

Job summary

ASTRAWAVE TECHNOLOGY in Singapore seeks an experienced analog mixed-signal layout and CAD designer to help develop high-speed RF solutions that complement our chip products.

You will collaborate with circuit designers to optimize layouts, perform physical verification, and drive layout quality from floorplanning to post-layout reviews. 6+ years in layout, Cadence expertise, and knowledge of AMS/RF layouts are essential.

Qualifications

• At least 6 years hands-on experience in layout engineering.
• Experience on technology nodes below 16nm.
• Experience with high-speed or RF layout.
• Proficiency with Cadence and pcell development (Perl/Python/Tcl).
• Strong understanding of AMS layout fundamentals, RC delay and decoupling caps.

Responsibilities

• Realize layout design from schematic presentations.
• Floor planning, device placement and power/signal routing.
• Perform DRC/LVS/ERC/ANT/ESD/PERC/LVL and physical verification.
• Ensure LVS and pass DRC rules; maintain layout quality.
• Assist post-layout adjustments and IP/block activities.
• Provide layout guidance to juniors and optimize methodologies.

Skills

RF layout

AMS layout fundamentals

layout design

signal integrity

Cadence

pcell development

automation scripting

Education

Diploma or Bachelor's in Electrical/Computer/Electronics Engineering

Tools

Cadence

Perl

Python

Tcl

Job description

ASTRAWAVE develops chips for data processing, IP licensing, networking, bus systems, and chiplet interconnects, as well as provides chip customization for different customers. We are currently seeking experienced analog mixed-signal layout and CAD designers to join our team in developing high-speed/RF solutions that will complement our current products.

The Person

Work closely with circuit design engineers to optimize layout to meet specification.

Team player and strong commitment to schedules.

Able to work in a multi-cultural environment.

Key Responsibilities

Realize layout design from schematic presentation.

Layout design implementation includes the following functions:

• Floor planning and device placement
• Power and Signal routings and Integrity optimization
• DRC/LVS/ERC/ANT/ESD/PERC/LVL and necessary Physical Verification
• Passing DRC rules and ensuring LVS
• Preparing material and reviewing of layout
• Checklist/Methodology to ensure quality of layout
• Layout methodology and enhancement

Participate in post layout adjustments and block/IP activities.

Good understanding of AMS layout fundamentals/EMIR/RC delay/DecouplingCaps/Latch-up.

Preferred Experience

Experience working on technology node below 16nm.

Experience working on high-speed or RF layout.

Experience in TX/RX/PLL/ADC/DAC/etc. is a plus.

Experience working with Cadence skills or equivalent tools for pcell development(perl/python/tcl) and automation to increase layout productivity.

Understanding of process technology and circuit design.

Understanding of analog layout physical verification CAD setup.

At least 6 years of hands-on working experience in layout engineering.

Experience working with leading industry CAD tools, methodology and finfet technology.

Experience with analog/digital on top (chip-top) integration is a plus point.

Providing layout guidance to juniors ensuring quality layouts.

Academic Credentials

Diploma or bachelor’s in electrical/computer/electronics engineering or equivalent.