Senior/Physical Design Engineer

Black Sesame Technologies (Singapore) Pte Ltd; Singapore; On-site; SGD 120,000 - 180,000; Full time

Job summary

Black Sesame Technologies (Singapore) Pte Ltd is seeking a Senior Physical Design Engineer to drive RTL-to-GDS implementation for complex semiconductor chips. You will focus on block-level timing closure, formal checks, and power analysis, while developing UPF-based power management strategies.

The role requires hands-on experience with advanced nodes (7nm/6nm/5nm), and proficiency in Synopsys and Cadence ARP tools.

Qualifications

• Bachelor’s degree required in Electrical or Computer Engineering or related field.
• Minimum 3 years hands-on experience in physical design for complex semiconductor chips.
• Strong experience with advanced process nodes (7nm/6nm/5nm).
• Proficiency in low power design and UPF usage.
• Experience with block-level APR, STA, PI, PV, FM, and VCLP using industry tools.
• Proficiency with Synopsys and Cadence ARP tools for physical design.
• Familiarity with Tcl, Perl, or Python for automation.
• Knowledge of automotive chip physical design and standards.

Responsibilities

• Manage full physical design process from RTL to GDS for complex chips.
• Achieve block-level timing closure by optimizing constraints and performing timing analysis.
• Perform formal checks to ensure functional and timing compliance.
• Conduct low power checks and analyze power consumption for optimization.
• Collaborate on UPF development for power management and control.
• Execute block-level APR, STA, PI, PV, FM, and VCLP signoffs.
• Leverage Synopsys and Cadence ARP tools for high-quality design.
• Develop automation scripts to streamline design flow.
• Apply automotive standards to physical design requirements.

Skills

Physical design

Timing closure

UPF

Scripting (Tcl)

Scripting (Perl)

Scripting (Python)

Synopsys tools

Cadence ARP

Block-level APR

STA

PV

FM

VCLP signoff

Education

Bachelor’s degree in Electrical Engineering/Computer Engineering

Tools

Synopsys

Cadence ARP

Job description

We are seeking a skilled Senior Physical Design Engineer to join our team. As a Senior Physical Design Engineer, you will be responsible for the entire process from RTL to GDS, ensuring the successful implementation of complex semiconductor chips. You will focus on block-level timing closure, formal checks, low power checks, power analysis, and signoff for block-level physical implementation. Your expertise in advanced process nodes, low-power design, and automotive chip physical design will contribute to the development of cutting-edge semiconductor products.

Responsibilities

• Manage the entire physical design process, including RTL to GDS implementation, for complex semiconductor chips.
• Achieve block-level timing closure by optimizing design constraints, performing timing analysis, and applying optimization techniques.
• Conduct formal checks to ensure the design adheres to functional and timing requirements.
• Perform low power checks and analyze power consumption to optimize power efficiency.
• Collaborate with the design team to develop and implement UPF (Unified Power Format) for power management and control.
• Conduct block-level Place and Route (APR), Static Timing Analysis (STA), Power Integrity (PI), Physical Verification (PV), Formal Verification (FM), and Voltage-Current-Latency-Power (VCLP) signoff.
• Utilize Synopsys and Cadence ARP (Automated Routing and Place) tools to achieve high-quality physical design.
• Develop and utilize scripts in Tcl, Perl, or Python to automate design tasks and enhance the design flow.
• Apply your expertise in automotive chip physical design to meet the specific requirements and standards of automotive applications.

Qualification/ Requirements

• Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related field.
• Minimum of 3 years of hands-on experience in physical design, working on complex semiconductor chips.
• Strong experience and understanding of advanced process nodes such as 7nm, 6nm, or 5nm.
• Proficiency in low power design techniques and hands-on experience with UPF.
• Experience with block-level APR, STA, PI, PV, FM, and VCLP, using industry-standard tools.
• Proficient with Synopsys and Cadence ARP tools for physical design.
• Familiarity with scripting languages such as Tcl, Perl, or Python for automation and design flow improvement.
• Knowledge and experience in automotive chip physical design, including compliance with automotive standards and requirements.