Physical Design Engineer

RICORE TECHNOLOGY PTE. LTD.; Singapore; On-site; SGD 90,000 - 150,000; Full time

Job summary

RICORE TECHNOLOGY PTE. LTD. is seeking a hands-on physical design engineer to lead top-level and block-level P&R activities, including floorplanning, clock and power distribution, and timing closure.

You will work with industry-standard EDA tools (DC, Genus, Innovus, ICC2, Calibre) and help develop flow, sign-off, and verification strategies, with emphasis on full-chip STA and DFT awareness. Singapore-based role with exposure to advanced process nodes.

Qualifications

• Bachelor's degree with at least 3 years of relevant experience.
• Hands-on physical-design back-end experience.
• Experience with mainstream EDA tools: DC, Genus, Innovus, ICC2, PT, STARRC, Redhawk, Calibre, VCLP.
• Strong scripting skills in TCL, Perl, csh and Makefile.
• Knowledge of Synthesis and DFT is a plus.
• Experience with Samsung 4 nm / 5 nm process preferred; sign-off on PT options and STA; full-chip STA.
• Familiarity with Volts / Redhawk sign-off criteria, flow setup and debugging.

Responsibilities

• Possess in‑depth understanding of top‑level / block‑level P&R implementation, including floorplan, clock & power distribution, timing closure, physical and electrical verification.

Skills

TCL scripting

Perl scripting

csh scripting

Makefile

Education

Bachelor's degree

Tools

DC

Genus

Innovus

ICC2

PT

STARRC

Redhawk

Calibre

VCLP

Job description

Job Responsibilities

Possess in‑depth understanding of top‑level / block‑level P&R implementation, including floorplan, clock & power distribution, timing closure, physical and electrical verification.

Job Requirements

• Bachelor's degree with minimum 3 years of relevant working experience.
• Solid hands‑on physical‑design back‑end experience. Familiar with mainstream industry EDA tools, capable of understanding tool capabilities and underlying algorithms, including DC, Genus, Innovus, ICC2, PT, STARRC, Redhawk and Calibre, VCLP etc.
• Strong scripting skills, proficient in common scripting languages such as TCL, Perl, csh and Makefile.
• Knowledge of Synthesis and DFT is a plus.
• Candidates with experience in one or more of the following areas are preferred:- Development of project implementation flow; hands‑on experience with Samsung 4 nm / 5 nm process.
• Sign‑off experience on PT options and STA; full‑chip STA experience.
• Familiarity with Volts / Redhawk sign‑off criteria, flow setup and debugging.