Physical Design Engineer (Advanced Node / ASIC / Full Flow Implementation)

DADACONSULTANTS PTE. LTD.; Singapore; On-site; SGD 70,000 - 100,000; Full time

Benefits offered by this job

Opportunity to work on cutting-edge semiconductor projects

Exposure to full-chip design flow

Competitive compensation and long-term growth opportunities

Job summary

DADACONSULTANTS PTE. LTD. is seeking an engineer for their expanding physical design team in Singapore. The role involves end-to-end physical design implementation for ASIC projects, engaging in key stages like floorplanning and timing closure.

Ideal candidates will have a Bachelor’s degree in Microelectronics or Electronic Engineering and familiarity with PnR tools such as ICC2 or Innovus. The position offers competitive compensation along with opportunities for long-term growth and exposure to cutting-edge semiconductor projects.

Qualifications

• Bachelor’s degree or above in Microelectronics, Electronic Engineering, or related fields.
• Understanding of physical design flow and IC development process.
• Familiarity with PnR tools such as ICC2, Fusion Compiler, or Innovus.

Responsibilities

• Perform end-to-end physical design implementation from netlist to GDSII.
• Work on key stages including floorplanning, power planning, and placement.
• Drive timing closure across MMMC scenarios.

Skills

Physical design flow understanding

Timing analysis

Power optimization

Scripting skills (TCL / Python / Shell)

Education

Bachelor’s degree in Microelectronics or Electronic Engineering

Tools

ICC2

Fusion Compiler

Innovus

Job description

My Client:

My client is a global technology company focused on advanced semiconductor and high-performance computing systems. The engineering team is dedicated to building next-generation ASIC solutions across advanced process nodes, supporting large-scale compute-intensive applications. The team operates in a highly technical and fast-paced environment, with strong emphasis on physical implementation, performance optimization, and full-chip delivery. They are currently expanding their physical design team to support growing project demands across advanced nodes.

Job Responsibilities:

• Perform end-to-end physical design implementation from netlist to GDSII for advanced ASIC projects.
• Work on key stages including floorplanning, power planning, placement, clock tree synthesis (CTS), routing, and optimization.
• Drive timing closure across MMMC scenarios, including setup/hold fixing, clock optimization, and ECO implementation.
• Conduct physical verification and signoff tasks (DRC, LVS, IR drop, EM analysis) to ensure tape-out readiness.
• Optimize power, performance, and area (PPA) through iterative design improvements.
• Collaborate closely with front-end design, DFT, and signoff teams to resolve integration and late-stage issues.
• Contribute to design methodology improvements and automation through scripting and tooling enhancements.

Job Requirements:

• Bachelor’s degree or above in Microelectronics, Electronic Engineering, or related fields.
• Understanding of physical design flow and IC development process.
• Familiarity with PnR tools such as ICC2, Fusion Compiler, or Innovus.
• Knowledge of timing analysis, power optimization, and physical verification concepts.
• Basic scripting skills (TCL / Python / Shell) for automation is a plus.
• Strong learning ability and willingness to work in advanced technology environments.

What They Offer:

• Opportunity to work on cutting-edge semiconductor projects at advanced technology nodes.
• Exposure to full-chip design flow and large-scale ASIC development.
• Competitive compensation and long-term growth opportunities.