Technical Manager – NPU Physical Design

MediaTek; Singapore; On-site; SGD 100,000 - 150,000; Full time

Benefits offered by this job

Attractive compensation and benefits package

Opportunity to grow into senior leadership positions

Job summary

MediaTek is seeking a Technical Manager (Physical Design) in Singapore to lead physical design projects and manage signoff activities for complex semiconductor products. The ideal candidate will have 8–12 years of experience, strong leadership skills, and deep technical expertise in EDA tools like Synopsys and Cadence. Join us to work on cutting-edge technologies in a collaborative environment with opportunities for career advancement and an attractive compensation package.

Qualifications

• 8–12 years of hands-on experience in physical design, including synthesis, PNR, STA, EMIR, and PV.
• Strong expertise with EDA tools.
• Proven track record of successful tapeouts for complex semiconductor products.

Responsibilities

• Lead and perform tasks in RTL synthesis, floorplanning, placement, clock tree synthesis, routing, and physical verification.
• Manage signoff activities including Static Timing Analysis, EMIR, and PV.
• Collaborate with cross-functional teams and drive project execution.

Skills

Leadership

Project Management

Communication Skills

Team Development

Education

Bachelor’s or Master’s degree in Electrical Engineering or Computer Engineering

Tools

Synopsys

Cadence

Siemens

Job description

We are seeking an accomplished and motivated Technical Manager (Physical Design) with 8–12 years of industry experience to join our team. This role demands deep technical expertise in all stages of the physical design flow—including synthesis, PNR, and signoff activities (STA, EMIR, and PV). In addition to technical competency, the ideal candidate will possess strong leadership and project management abilities, successfully guiding a team of engineers through complex project executions.

What you will do

• Lead and perform tasks in RTL synthesis, floorplanning, placement, clock tree synthesis, routing, and physical verification.
• Manage signoff activities including Static Timing Analysis (STA), EMIR, and Physical Verification (PV) to ensure tapeout-quality designs.
• Collaborate with cross-functional teams (DFT, RTL, STA, Packaging) to drive seamless integration and execution.
• Plan, monitor, and execute project execution, set deadlines, track milestones, and report progress to leadership.
• Guide, mentor, and develop the team, fostering technical excellence and a collaborative environment.
• Troubleshoot and resolve design challenges, proactively communicating risks and mitigation strategies.
• Interface with EDA vendors and keep up-to-date with industry trends, tools, and methodologies.
• Prepare and deliver technical presentations, document processes, and contribute to organizational knowledge base.

Main Requirements and Qualifications

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering.
• 8–12 years of hands‑on experience in physical design, including synthesis, PNR, STA, EMIR, and PV.
• Strong expertise with EDA tools: Synopsys, Cadence, or Siemens (e.g., Design Compiler, IC Compiler, Fusion Compiler, Genus, Innovus, PrimeTime, Voltus, Calibre).
• Proven track record of successful tapeouts for complex semiconductor products.
• Solid understanding of power, performance, area (PPA) optimization techniques.
• Excellent project management skills, including resource planning, task tracking, and team leadership.
• Strong communication and interpersonal skills; ability to present technical material and interact confidently with cross‑functional teams.
• Experience leading and mentoring engineers.
• Familiarity with advanced process nodes (3 nm, 2 nm)

Why Join Us?

• Work on cutting‑edge semiconductor products in a collaborative and high‑performance environment.
• Opportunity to grow into senior leadership positions.
• Attractive compensation and benefits package.