Physical Design Engineer

BITMAIN; Singapore; On-site; SGD 120,000 - 170,000; Full time

Job summary

BITMAIN in Singapore is seeking a senior IC design engineer to drive digital physical design from RTL to GDS, perform full-chip STA signoff, and contribute to signoff standards and SPICE timing simulations for critical paths.

You will develop and maintain PR/PV/PI/STA design flows, support advanced nodes and EDA tool sets, and participate in PPA and yield optimization through tool development and flow improvements.

Qualifications

• Proficient in complete digital physical design flow (RTL to GDS) and related EDA tools (INVS, FC, PT, PX, RH, Calibre, etc.)
• Strong expertise in STA analysis methods and flows
• Familiar with DC or FC synthesis processes
• Tape-out experience with ultra-low-voltage, large-scale, or complex IP chips is a strong advantage
• Familiar with low-power design methodologies and power analysis flows

Responsibilities

• Responsible for digital circuit physical implementation (RTL to GDS) and PV/PI signoff; perform full-chip STA signoff, participate in defining STA signoff standards, and conduct SPICE simulation for critical timing paths
• Develop, optimize, and maintain PR/PV/PI/STA design flows; support the introduction of advanced technology nodes and EDA tools
• Participate in PPA (Power, Performance, Area) and yield optimization, including related tool development and flow improvement

Skills

Digital physical design flow

STA analysis methods

Scripting languages (Tcl, Python, Perl

3D IC design experience

Tape-out experience

Tools

Calibre

DC synthesis

FC synthesis

INVS

Python scripting

Job description

1. Responsible for digital circuit physical implementation (RTL to GDS) and PV/PI signoff; perform full-chip STA signoff, participate in defining STA signoff standards, and conduct SPICE simulation for critical timing paths; 2. Develop, optimize, and maintain PR/PV/PI/STA design flows; support the introduction of advanced technology nodes and EDA tools; 3. Participate in PPA (Power, Performance, Area) and yield optimization, including related tool development and flow improvement.

Requirement

1. Proficient in the complete digital physical design flow (RTL to GDS) and related EDA tools (INVS, FC, PT, PX, RH, Calibre, etc.); strong expertise in STA analysis methods and flows; familiar with DC or FC synthesis processes; 2. Experience in top-level PR/PI/PV/BUMP or ESD planning is a plus; familiarity with signoff standards for advanced process nodes is preferred; proven tape-out experience with ultra-low-voltage, large-scale, or complex IP chips is a strong advantage; 3. Familiar with low-power design methodologies and power analysis flows; experience in PPA optimization preferred; 4. Strong programming skills in one or more languages such as Tcl, Python, Perl, C, or C++; 5. Familiar with 3D IC design; relevant experience is a plus; 6. Prior experience with STA signoff in tape-out projects is preferred.