Memory Design Staff Engineer: Ultra-Low Power SoCs

Search Staffing Pte Ltd; Singapore; On-site; SGD 120,000 - 180,000; Full time

Job summary

Search Staffing Pte Ltd is assisting a US-based pioneer to fill a Memory Design Staff Engineer role in Singapore. The candidate will work on embedded SRAM and Register File IPs for ultra-low-power SoCs, including SRAM compiler development and memory peripheral circuits.

Close collaboration with architecture, physical design, foundry, EDA vendors, and silicon validation teams is essential. The role emphasizes design across conventional, near-threshold, and sub-threshold voltage ranges, with

Qualifications

• Experience in embedded SRAM or Register File IP for advanced 12nm FINFET tech.
• Hands-on SRAM compiler development and configurable memory generation.
• Strong scripting in Python, Tcl or Perl.

Responsibilities

• Design ultra-low power embedded SRAM and Register File IPs for SoCs.
• Develop SRAM compiler architectures for multiple memory configurations.
• Design memory peripherals like sense amplifiers, decoders and drivers.
• Optimize designs for area, performance, leakage, dynamic power; compare with silicon data.
• Analyze low-voltage failure mechanisms and margins.
• Develop automation scripts to improve compiler generation and testing.
• Collaborate with memory architecture, PD, timing/STA, DFT, foundry and EDA teams.
• Support memory IP integration from architecture to production release.

Skills

SRAM architecture

Memory compiler design

Circuit design

Python scripting

Verilog/VHDL

Cadence tools

Debugging

Cross-functional collaboration

Education

Electrical Engineering degree

Tools

Cadence Virtuoso

Cadence Spectre

HSPICE

Liberate MX

Monte Carlo simulations

Job description

Search Staffing Pte Ltd is assisting a US-based pioneer to fill a Memory Design Staff Engineer role in Singapore. The candidate will work on embedded SRAM and Register File IPs for ultra-low-power SoCs, including SRAM compiler development and memory peripheral circuits.

Close collaboration with architecture, physical design, foundry, EDA vendors, and silicon validation teams is essential. The role emphasizes design across conventional, near-threshold, and sub-threshold voltage ranges, with