Senior Memory Layout Engineer (Submicron IC)

Broadcom; Singapore; On-site; SGD 120,000 - 180,000; Full time

Job summary

Broadcom is seeking a Staff Layout Engineer to work in Singapore, focusing on memory, I/O, and standard cell layouts in the Library Group within Central Engineering. The role requires strong Cadence layout skills and experience with verification tools, with relocation to Singapore required.

Ideal candidates will have extensive experience in submicron CMOS processes and be able to lead layout projects, collaborate across teams, and contribute to continuous improvement of layout methodologies.

Qualifications

• Minimum 8 years of hands-on IC layout experience.
• Strong knowledge of submicron processes (16nm/7nm/5nm/2nm and below).
• Experience in memory, I/O and standard cell layouts; analog layout a plus.

Responsibilities

• Understand and apply all layout guidelines and process rules.
• Schedule timeline and layout floor-planning.
• Deliver quality layout and verification within plan, with minimal supervision.
• Collaborate within the Library Group and communicate effectively.

Skills

Cadence layout

Cadence schematic capture

CALIBRE verification

Hercules verification tools

Memory layout knowledge

Digital layout

Analog layout (plus)

Team leadership

Tools

Cadence Virtuoso

CALIBRE

Job description

Broadcom is seeking a Staff Layout Engineer to work in Singapore, focusing on memory, I/O, and standard cell layouts in the Library Group within Central Engineering. The role requires strong Cadence layout skills and experience with verification tools, with relocation to Singapore required.

Ideal candidates will have extensive experience in submicron CMOS processes and be able to lead layout projects, collaborate across teams, and contribute to continuous improvement of layout methodologies.