Senior I/O Design Engineer - Analog & Mixed-Signal

AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED; Singapore; On-site; SGD 120,000 - 180,000; Full time

Job summary

Broadcom’s I/O Design team in Singapore seeks an experienced I/O Design Engineer with a strong analog/mixed-signal background. You will contribute to design and verification of IPs and I/Os, including AI programs on advanced nodes, in a collaborative, growth‑oriented environment.

Key duties: CMOS I/O, bandgap references, op-amps and POR circuits; run simulations for AC/DC, SI and jitter; EMIR analysis; collaborate with layout; develop Verilog, Liberty and IBIS models; and prepare datasheets and

Qualifications

• MS or PhD in Electrical Engineering.
• 6+ years of I/O or analog circuit design experience.
• Deep proficiency in Cadence Virtuoso Schematic/Layout capture and SPICE/Spectre circuit simulation.
• Solid foundation in I/O protocols including GPIO, I2C, I3C, eMMC, RGMII and SPMI.
• Familiarity with ESD, EMI and Signal Integrity.
• Experience with advanced CMOS FinFET and GAA process nodes, including features, technology limitations and PPA tradeoffs.

Responsibilities

• Design CMOS I/O, high-precision bandgap references, op-amps, comparators and POR circuits.
• Run simulations to validate AC/DC performance, signal integrity, jitter and power.
• Perform transistor reliability and EMIR analysis.
• Work closely with layout teams to oversee physical design and verification.
• Build Verilog, Synopsys Liberty and IBIS models.
• Create and maintain detailed technical documentation, including datasheets, application notes and integration guides.
• Support chip-level integration and silicon bring-up in test chips and customer products.

Skills

I/O design

Analog circuit design

Mixed-signal design

Cadence Virtuoso

SPICE/Spectre

Verilog

Education

MS or PhD in Electrical Engineering

Tools

Cadence Virtuoso

Synopsys Liberty

IBIS modeling

Job description

Broadcom’s I/O Design team in Singapore seeks an experienced I/O Design Engineer with a strong analog/mixed-signal background. You will contribute to design and verification of IPs and I/Os, including AI programs on advanced nodes, in a collaborative, growth‑oriented environment.

Key duties: CMOS I/O, bandgap references, op-amps and POR circuits; run simulations for AC/DC, SI and jitter; EMIR analysis; collaborate with layout; develop Verilog, Liberty and IBIS models; and prepare datasheets and