Senior I/O & Analog Design Engineer for AI Projects

Broadcom Singapore Pte Ltd; Singapore; On-site; SGD 120,000 - 180,000; Full time

Job summary

Broadcom Singapore Pte Ltd is seeking an experienced I/O Design Engineer with a strong background in analog and mixed-signal IC design. You will contribute to design and verification of IP and I/Os, including AI programs on advanced nodes, in a collaborative team environment.

You will design CMOS I/O, run simulations, verify measurements, and work with layout to ensure physical design integrity while building Verilog and IBIS models and creating comprehensive documentation for integration and

Qualifications

• MS or PhD in Electrical Engineering.
• 6+ years of I/O or analog circuit design experience.
• Proficient with Cadence Virtuoso for schematic/layout and SPICE/Spectre simulations.
• Familiar with I/O protocols including GPIO, I2C, I3C, eMMC, RGMII and SPMI.

Responsibilities

• Design CMOS I/O, high-precision bandgap references, op-amps, comparators and POR circuits.
• Run simulations to validate AC/DC performance, signal integrity, jitter and power.
• Perform transistor reliability and EMIR analysis.
• Work closely with layout teams to oversee physical design and verification.
• Build Verilog, Synopsys Liberty and IBIS models.
• Create and maintain detailed technical documentation, including datasheets, application notes and integration guides.
• Support chip-level integration and silicon bring-up in test chips and customer products.

Skills

I/O Design

Analog/Mixed-Signal

Circuit Simulation

Documentation

Modeling

Education

MS or PhD in Electrical Engineering

Tools

Cadence Virtuoso

SPICE/Spectre

Verilog

Synopsys Liberty

IBIS models

Job description

Broadcom Singapore Pte Ltd is seeking an experienced I/O Design Engineer with a strong background in analog and mixed-signal IC design. You will contribute to design and verification of IP and I/Os, including AI programs on advanced nodes, in a collaborative team environment.

You will design CMOS I/O, run simulations, verify measurements, and work with layout to ensure physical design integrity while building Verilog and IBIS models and creating comprehensive documentation for integration and