I/O Design Engineer

Avago Technologies Intl' Sales Pte Ltd; Singapore; On-site; SGD 120,000 - 180,000; Full time

Job summary

Broadcom's Central Engineering Group seeks an I/O Design Engineer with experience in analog and mixed-signal IC design, to contribute to design and verification of IPs and I/Os for AI programs on advanced nodes. Join a world-class, collaborative team in Singapore, with growth opportunities.

Responsibilities include designing CMOS I/O, running simulations for SI/Power, and building models. Collaboration with layout and documentation work are essential for silicon bring-up and integration.

Qualifications

• MS or PhD in Electrical Engineering.
• 6+ years of I/O or analog circuit design experience.
• Proficiency with Cadence Virtuoso Schematic/Layout and SPICE/Spectre simulations.
• Knowledge of I/O protocols: GPIO, I2C, I3C, eMMC, RGMII, SPMI.

Responsibilities

• Design CMOS I/O, bandgap references, op-amps, comparators and POR circuits.
• Run simulations to validate AC/DC performance, signal integrity, jitter and power.
• Perform transistor reliability and EMIR analysis.
• Collaborate with layout teams to oversee physical design and verification.
• Build Verilog, Synopsys Liberty and IBIS models.
• Create and maintain datasheets, application notes and integration guides.
• Support chip-level integration and silicon bring-up in test chips and customer products.

Skills

Cadence Virtuoso

SPICE/Spectre

Verilog modelling

GPIO

I2C

I3C

eMMC

RGMII

SPMI

Signal Integrity

ESD/EMI

FinFET/GAA

PPA tradeoffs

Education

MS in Electrical Engineering

PhD in Electrical Engineering

Tools

Verilog

IBIS models

Liberty models

Job description

Role Overview

Broadcom’s Central Engineering Group is seeking an I/O Design Engineer with experience in analog and mixed-signal IC design. The candidate will contribute to the design and verification of a broad range of IP and I/Os, including leading-edge AI programs on advanced nodes. Joining a world-class team of engineers with a highly collaborative culture, the role offers opportunities for growth and development.

Responsibilities

• Design of CMOS I/O, high-precision bandgap references, op-amps, comparators and power-on-reset circuits.
• Run simulations to validate AC/DC performance, signal integrity, jitter and power.
• Perform transistor reliability and EMIR analysis.
• Work closely with layout teams to oversee physical design and verification.
• Build Verilog, Synopsys Liberty and IBIS models.
• Create and maintain detailed technical documentation, including datasheets, application notes and integration guides.
• Support chip-level integration and silicon bring-up in test chips and customer products.

Technical Skills and Requirements

• MS or PhD in Electrical Engineering.
• 6+ years of I/O or analog circuit design experience.
• Deep proficiency in Cadence Virtuoso Schematic/Layout capture and SPICE/Spectre circuit simulation.
• Solid foundation in I/O protocols includingGPIO, I2C, I3C, eMMC, RGMII and SPMI.
• Familiarity with ESD, EMI and Signal Integrity.
• Experience with advanced CMOS FinFET and GAA process nodes, including features, technology limitations and PPA tradeoffs.