Senior I/O & Analog IC Design Engineer

Broadcom; Singapore; On-site; SGD 120,000 - 180,000; Full time

Job summary

Broadcom's Central Engineering Group in Singapore is seeking an experienced I/O Design Engineer to contribute to analog and mixed-signal IC design across IP and I/Os.

You will run simulations, verify AC/DC performance, ensure signal integrity, and collaborate with layout teams. The role involves documenting designs, building models, and supporting silicon bring-up on advanced nodes. A strong background in Cadence tools is essential.

Qualifications

• MS or PhD in Electrical Engineering.
• 6+ years of I/O or analog circuit design experience.
• Deep proficiency in Cadence Virtuoso Schematic/Layout capture and SPICE/Spectre circuit simulation.
• Solid foundation in I/O protocols including GPIO, I2C, I3C, eMMC, RGMII and SPMI.
• Familiarity with ESD, EMI and Signal Integrity.
• Experience with advanced CMOS FinFET and GAA process nodes, including features, technology limitations and PPA tradeoffs.

Responsibilities

• Design of CMOS I/O, high-precision bandgap references, op-amps, comparators and power-on-reset circuits.
• Run simulations to validate AC/DC performance, signal integrity, jitter and power.
• Perform transistor reliability and EMIR analysis.
• Work closely with layout teams to oversee physical design and verification.
• Build Verilog, Synopsys Liberty and IBIS models.
• Create and maintain detailed technical documentation, including datasheets, application notes and integration guides.
• Support chip-level integration and silicon bring-up in test chips and customer products.

Skills

I/O design

Analog circuit design

EMIR analysis

Education

MS or PhD in Electrical Engineering

Tools

Cadence Virtuoso

SPICE/Spectre

Verilog

Synopsys Liberty

IBIS models

Job description

Broadcom's Central Engineering Group in Singapore is seeking an experienced I/O Design Engineer to contribute to analog and mixed-signal IC design across IP and I/Os.

You will run simulations, verify AC/DC performance, ensure signal integrity, and collaborate with layout teams. The role involves documenting designs, building models, and supporting silicon bring-up on advanced nodes. A strong background in Cadence tools is essential.