Senior I/O & Analog Design Engineer for Silicon AI

AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED; Singapore; On-site; SGD 120,000 - 180,000; Full time

Job summary

Broadcom Inc. is seeking an experienced I/O Design Engineer to design and verify analog and mixed-signal ICs, contributing to advanced AI programs within the Central Engineering Group.

You will design CMOS I/O circuits, run simulations for AC/DC performance and signal integrity, perform EMIR analysis, collaborate with layout teams, and develop Verilog, IBIS models, and documentation to support integration and bring-up.

Qualifications

• Master’s or PhD in Electrical Engineering.
• 6+ years in I/O or analog circuit design.
• Proficiency in Cadence Virtuoso and SPICE/Spectre.

Responsibilities

• Design CMOS I/O circuits, high-precision bandgap references, operational amplifiers, comparators, and power-on-reset circuits.
• Run simulations to validate AC/DC performance, signal integrity, jitter, and power consumption for circuit reliability.
• Perform transistor reliability and electromigration (EMIR) analysis to ensure device robustness.
• Collaborate with layout teams to oversee physical design and verify adherence to specifications.
• Develop Verilog, Synopsys Liberty, and IBIS models to support design integration and verification.
• Create and maintain comprehensive technical documentation including datasheets, application notes, and integration guides for internal and customer use.
• Support chip-level integration and silicon bring-up activities for test chips and customer products to ensure successful deployment.

Skills

I/O/analog circuit design

I/O protocols (GPIO, I2C, I3C, eMMC, R

Signal integrity & EMI/ESD

CMOS FinFET/GAA process knowledge

Education

Master’s or PhD in Electrical Engineering

Tools

Cadence Virtuoso

SPICE/Spectre

Job description

Broadcom Inc. is seeking an experienced I/O Design Engineer to design and verify analog and mixed-signal ICs, contributing to advanced AI programs within the Central Engineering Group.

You will design CMOS I/O circuits, run simulations for AC/DC performance and signal integrity, perform EMIR analysis, collaborate with layout teams, and develop Verilog, IBIS models, and documentation to support integration and bring-up.