Senior Engineer - Integration Engineering

INFINEON TECHNOLOGIES ASIA PACIFIC PTE LTD; Singapore; On-site; SGD 80,000 - 120,000; Full time

Job summary

INFINEON TECHNOLOGIES ASIA PACIFIC PTE LTD in Singapore seeks a skilled engineer to advance mixed-signal IP integration within a high-performance R&D setting. You will drive integration methods for analog/digital blocks and partner with subsystem/SoC teams to optimize power and timing strategies.

Requires 3–5 years in digital/analog/mixed-signal design, proficiency with Cadence Virtuoso or RTL2GDS, and strong debugging and customer-facing skills. Excellent English communication is mandatory.

Qualifications

• University degree in Electrical/Electronics Engineering, CS or equivalent.
• 3–5+ years in digital, analog, or mixed-signal design.
• Hands-on with Cadence Virtuoso or RTL2GDS tools.

Responsibilities

• Work in the R&D Mixed-Signal IC design organization.
• Enable Mixed-Signal IP Integration into Sub-System/SoC per customer requirements.
• Collaborate with subsystem/SoC teams on power/timing/netlisting strategy for IP integration.
• Define IP integration method for analog/digital or mixed-signal blocks.
• Debug and resolve issues in mixed-signal IP integration.
• Drive improvements of integration methodologies and guide IP designers.

Skills

Digital/mixed-signal design

Debugging skills

English communication

Customer-oriented mindset

Programming/scripting (Perl/TCL/Python

Education

Bachelor/Master in Electrical/Electronics Engineering or CS

Tools

Cadence Virtuoso

Cadence/Synopsys RTL2GDS

Unix/Linux

Job description

Your role

Key responsibilities in your new role

• Work in the R&D Mixed-Signal IC design organization
• Become a key enabler for Mixed-Signal IP Integration into the Sub-System or System on Chip (SoC), with regards to requested design views from the customer
• Act closely with the subsystem/SoC teams on the right power/timing/netlisting strategy for IP integration
• Define the proper IP integration method for analog/digital or mixed-signal blocks
• Debug and solve issues with regards to mixed-signal IP integration
• Drive improvements of the state-of-the-art mixed-signal IP delivery methodologies
• Guide and support IP designers for usage of the state-of-the-art integration methods

Your profile

Qualifications and skills to help you succeed

• A university bachelor or master degree in Electrical/Electronics Engineering, Computer Science, or equivalent
• At least 3-5 years of experience in digital, analog, or mixed-signal design
• Experience with Cadence Virtuoso or Cadence/Synopsys RTL2GDS tools
• Experience with CAD methodology for digital and/or analog design and integration
• Knowledge of UPF and Digital IP power strategy
• Programming or scripting skills such as Perl, TCL, Python, or Skill is a plus
• Knowledge of HDL languages (System Verilog, VHDL) and experience with Unix/Linux
• Strong debugging skills
• Solid networking and customer-oriented soft skills
• Good English verbal and written skills are mandatory