Analog Design Engineer

CURIOUS TEK PTE. LTD.; Singapore; On-site; SGD 120,000 - 180,000; Full time

Job summary

CURIOUS TEK PTE. LTD. is seeking a senior analog design engineer to design and implement mixed-signal CMOS IP.

The role covers the full development cycle from circuit design and simulation to verification and bench characterization, focusing on high-speed Serdes and sub-micron CMOS technologies. The ideal candidate has a strong background in high-speed analog design, significant experience with SPICE tools, and the ability to work independently while collaborating with a team in a fast-paced

Qualifications

• Bachelor or above degree in Microelectronic or Electronic and Information Engineering.
• 5+ years of experience in analog design.
• Strong knowledge of high-speed Serdes (PLL, CDR, CTLE/DFE, TX driver).

Responsibilities

• Design and implementation of mixed signal CMOS IP.
• Development cycle including circuit design, simulation, modeling, verification and bench characterization.
• Managing products utilizing leading-edge sub-micron CMOS technologies (5/6nm).
• Developing state of the art high speed mixed signal IP products that include op amps, comparators, bandgap, low-drop linear regulator, ADCs, DC-DC converters, and high bit-rate Gbps Serdes TX/RX.

Skills

Strong communication skills

Independence

Team player

Education

Bachelor or above degree in Microelectronic or Electronic and Information Engineering

Tools

Cadence Spectre

Synopsys Custom Compiler

Calibre

Job description

Job Responsibilities:

• Design and implementation of mixed signal CMOS IP. Development cycle including circuit design, simulation, modeling, verification and bench characterization.
• Management products utilizing leading edge sub-micron CMOS technologies, e.g., 5/6nm
• Developing state of the art high speed mixed signal IP products that include op amps, comparators, bandgap, low-drop linear regulator, ADCs, DC-DC converters, and high bit-rate (Gbps) Serdes TX/RX.

Requirements:

• Bachelor or above degree in Microelectronic or Electronic and Information Engineering
• 5 years or above experience in the area of analog design
• Good knowledge in analog IC design in high speed Serdes, e.g., PLL, CDR, CTLE/DFE, TX driver etc.

• Solid understanding and experience in key analog layout considerations such as device matching, parasitic, noise coupling, floor planning, sensitive signal routing, current density and reliability considerations
• Familiar with SPICE simulation tool (e.g., Cadence spectre, Synopsys Custom Compiler, Calibre)

• Strong Communication skills, high level of independence, self-motivation and good team player