Analog/Mixed Signal IC Design Engineer

AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED; Singapore; On-site; SGD 120,000 - 180,000; Full time

Job summary

AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED is seeking a senior IC design engineer to drive high-speed analog/mixed-signal IP development for use in AI, ML, HPC, and hyperscale data centers.

You will design, verify and optimize high-speed circuits, participate in IP integration into SoCs, and support silicon bring-up with a strong emphasis on first-time-right quality.

Qualifications

• Bachelor/Master/PhD in Electrical/Electronic Engineering with 10+ years of related experience preferred.
• Extensive experience in high-speed analog/digital circuits including Serdes, HBM and UCIe.
• Proficient with Cadence Virtuoso for schematic, layout and verification; knowledge of Spectre and ADE tools.

Responsibilities

• Design, pre-layout and post-layout verification of high-speed circuits for IPs.
• Develop schematics, perform layout reviews, and run detailed simulations.
• Optimize circuits for low jitter and low power in high-speed paths.
• Conduct design reviews, prepare slides, and document results.
• Assist IP integration into SOCs and support silicon bring-up and debugging.

Skills

High-speed circuit design

Serdes design

Design for verification

Communication of technical concepts

Fast problem solving

Education

Electrical/Electronic Engineering (Bachelor/Master/PhD)

Tools

Cadence Virtuoso

Spectre

ADE Explorer/Assembler

MATLAB

3D modeling

Job description

This position is part of a highly skilled multi-geographical team tasked with the development of high speed analog, mixed-signal IPs covering HBM, UCIe, and many others areas using the latest A14, 2nm and 3nm CMOS technology. The team will be developing key differentiating IPs used in the Artificial Intelligence, Machine Learning, High Performance Computing and Hyper-Scale Data Center markets. Each member of the team is expected to be committed to the team success, create new innovation, and ensure customer usage satisfaction with first time right quality mindset.

Responsibilities:

Design, pre-layout and post-layout verification of circuits to be used as part of state-of-the-art integrated circuits including:

• High speed mixed-signal design
• High speed clock distribution networks
• High speed RX & TX s design

This role involves

• Developing circuit schematics, performing detailed layout reviews and performing all necessary verification/simulations.
• Optimizing circuits in high speed paths for low jitter and low power.
• Conducting design reviews and creating slides and other associated documentation.
• Assisting IP integration into SOCs
• Providing guidance to validation engineers or be involve in initial silicon bring-up, debug, and characterization

Knowledge and Experience:

• The position requires extensive experience with designing high-speed custom analog and digital circuits in area(s) like Serdes, HBM, UCIe and PLL.
• The candidate should be extremely familiar with the use of the Cadence Virtuoso tool suite to design and verify high-speed custom circuits, including
• Virtuoso schematic capture and layout & Spectre circuit simulator.
• Virtuoso Analog Design Environment (ADE) - Explorer, Assembler, etc.
• Design experience in advanced CMOS nodes is required; FinFET design experience is a plus.
• The ideal candidate will have wide-ranging experience, with a demonstrated ability to rely on both thorough understanding of engineering fundamentals and design creativity to solve circuit design problems.
• Candidate with the follow ability will be advantages:
• Demonstrated ability to clearly present their work to other circuit designers and to non-experts as well.
• Ability to perform matlab, AMI or 3D modeling of their highspeed design.
• Good knowledge of industry standard interface specification and show the ability to explain/reason on the high speed design definition(s).

Education:

• Bachelor/Master/PhD in Electrical/Electronic Engineering with 10+ years of related experience is preferred.