Senior Engineer/ Engineer ( Thin Film -CMP Process)

Vanguard International Semiconductor Corporation; Singapore; On-site; SGD 60,000 - 90,000; Full time

Job summary

Vanguard International Semiconductor Corporation in Singapore seeks a disciplined Engineer to analyze SPC charts for SPACE rules and yield improvement. You will work with JMP, Klarity ACE, PROMIS, and metrology tools to maintain quality and drive team-based problem solving across modules.

The role requires a degree in a relevant field and 2+ years in Thin Film CMP; strong communication, ownership, and analytical skills are essential for success in a fast-paced manufacturing environment.

Qualifications

• Bachelor-level degree in a relevant engineering or science field.
• 2+ years of experience in Thin Film CMP processing.
• Ability to work in a fast-paced environment and under pressure.
• Strong communication and written skills.
• Proficient in MS Office applications.

Responsibilities

• Analyze SPC charts and apply SPACE rules; annotate to maintain quality troubleshooting rate.
• Analyze split lot, DOE data, ET, and sort yield using JMP, Klarity ACE.
• Create SPC charts and modify SLDB using PROMIS (Si-View).
• Upload and verify recipes; ensure content compliance using RMS.
• Lead junior engineers and support cross-functional teams for yield improvement.
• Troubleshoot recipe/ metrology tools; drive uptime and OEE.
• Lead small cross-functional teams on yield improvements and excursions.
• Engage in cross-fab benchmarking and update TS16949-aligned documentation.

Skills

Team player

Interpersonal skills

Analytical skills

Written skills

MS Office proficiency

Logical thinking

Ownership & accountability

Education

Degree in Electrical / Electronics / Microelectronics / Chemical Processing / Chemistry / Physics / Material Sciences / Mechanical

Tools

PROMIS (Si-View)

JMP

Klarity ACE

Job description

Job Responsibilities:

• Analyze SPC charts using SPACE. Know all the PR rules and their significance. Do proper annotation to maintain quality troubleshooting rate for SPC OOC. Understand Cp and Cpk indices.
• Analyze split lot, DOE data, ET, sort yield using JMP, Klarity ACE.
• Create SPC charts, DCOP and modify SLDB using PROMIS (Si-View).
• Upload recipe, check recipe and ensure recipe content compliance using RMS.
• Follow up on SPSR, MRB, 8D, TECN, or spec update with ECN. Provide guidance to junior Engineers.
• Setup and troubleshoot issues in recipes/ job files in all metrology tools within the Module.
• Analyze data from passed down to identify chronic process issues, establish improvement programs and lead engineers to resolve them. Establish CAS / procedures to be followed and work with other departments for resolution if required.
• Work as a team with both Equipment and Manufacturing Engineers to meet Module objectives. Drive team to meet key indices of Uptime and OEE as per the goals set for these indices.
• Take on leadership roles to drive a small cross functional task team to address yield improvement/ excursion issues.
• Facilitate/ initiate CIP programs to optimize process window, cost, yield, and productivity. Establish plans and strategies to optimize process capability to meet operational requirements.
• Resolve complex technical issues in own Module or yield related issues
• Follow up with cross-fab benchmarking activities to engage the best-in-campus practices across fabs.
• Self audit and update specifications / documentation to meet TS16949 Quality Standard requirements.

Requirements:

• Degree in Electrical / Electronics / Microelectronics / Chemical Process / Chemistry / Physics / Material Sciences / Mechanical
• Min 2 years of relevant work experience in Thin Film CMP Process
• An excellent team player with good interpersonal, communication and written skills
• Strong logical thinking capability and good analytical skill
• Highly committed with good ownership and accountability
• Able to adapt in a fast pace environment and work under pressure
• Proficient in MS Office Applications