Senior Engineer/ Engineer, Thin Film CMP Process

Vanguard International Semiconductor Corporation (VIS); Singapore; On-site; SGD 70,000 - 110,000; Full time

Job summary

Vanguard International Semiconductor Corporation (VIS) in Singapore seeks a CMP Process Engineer with 2+ years of Thin Film CMP experience to analyze SPC charts, manage recipes, and drive yield improvements. You will work with metrology tools, troubleshoot process issues, and lead cross-functional teams to optimize uptime and OEE in a fast-paced environment.

The role requires a degree in a related field and strong analytical, communication, and ownership skills.

Qualifications

• Min 2 years of relevant work experience in Thin Film CMP Process.
• Degree in Electrical / Electronics / Microelectronics / Chemical Process / Chemistry / Physics / Material Sciences / Mechanical.
• Excellent team player with good interpersonal, communication and written skills.
• Strong logical thinking capability and good analytical skill.
• Highly committed with good ownership and accountability.
• Able to adapt in a fast pace environment and work under pressure.

Responsibilities

• Analyze SPC charts using SPACE. Know all the PR rules and their significance. Do proper annotation to maintain quality troubleshooting rate for SPC OOC.
• Analyze split lot, DOE data, ET, sort yield using JMP, Klarity ACE.
• Create SPC charts, DCOP and modify SLDB using PROMIS (Si-View).
• Upload recipe, check recipe and ensure recipe content compliance using RMS.
• Follow up on SPSR, MRB, 8D, TECN, or spec update with ECN. Provide guidance to junior Engineers.
• Setup and troubleshoot issues in recipes/ job files in all metrology tools within the Module.
• Analyze data from passed down to identify chronic process issues, establish improvement programs and lead engineers to resolve them. Establish CAS / procedures to be followed and work with other departments for resolution if required.
• Work as a team with both Equipment and Manufacturing Engineers to meet Module objectives. Drive team to meet key indices of Uptime and OEE as per the goals set for these indices.
• Take on leadership roles to drive a small cross functional task team to address yield improvement/ excursion issues.
• Facilitate/ initiate CIP programs to optimize process window, cost, yield, and productivity. Establish plans and strategies to optimize process capability to meet operational requirements.
• Resolve complex technical issues in own Module or yield related issues
• Follow up with cross-fab benchmarking activities to engage the best-in-campus practices across fabs.
• Self audit and update specifications / documentation to meet TS16949 Quality Standard requirements.

Skills

Team player

Interpersonal skills

Written communication

Analytical skills

Ownership & accountability

Adaptability

Education

Degree in Electrical / Electronics / Microelectronics / Chemical Process / Chemistry / Physics / Material Sciences / Mechanical

Job description

• Analyze SPC charts using SPACE. Know all the PR rules and their significance. Do proper annotation to maintain quality troubleshooting rate for SPC OOC. Understand Cp and Cpk indices.
• Analyze split lot, DOE data, ET, sort yield using JMP, Klarity ACE.
• Create SPC charts, DCOP and modify SLDB using PROMIS (Si-View).
• Upload recipe, check recipe and ensure recipe content compliance using RMS.
• Follow up on SPSR, MRB, 8D, TECN, or spec update with ECN. Provide guidance to junior Engineers.
• Setup and troubleshoot issues in recipes/ job files in all metrology tools within the Module.
• Analyze data from passed down to identify chronic process issues, establish improvement programs and lead engineers to resolve them. Establish CAS / procedures to be followed and work with other departments for resolution if required.
• Work as a team with both Equipment and Manufacturing Engineers to meet Module objectives. Drive team to meet key indices of Uptime and OEE as per the goals set for these indices.
• Take on leadership roles to drive a small cross functional task team to address yield improvement/ excursion issues.
• Facilitate/ initiate CIP programs to optimize process window, cost, yield, and productivity. Establish plans and strategies to optimize process capability to meet operational requirements.
• Resolve complex technical issues in own Module or yield related issues
• Follow up with cross-fab benchmarking activities to engage the best-in-campus practices across fabs.
• Self audit and update specifications / documentation to meet TS16949 Quality Standard requirements.

Requirements:

• Degree in Electrical / Electronics / Microelectronics / Chemical Process / Chemistry / Physics / Material Sciences / Mechanical
• Min 2 years of relevant work experience in Thin Film CMP Process
• An excellent team player with good interpersonal, communication and written skills
• Strong logical thinking capability and good analytical skill
• Highly committed with good ownership and accountability
• Able to adapt in a fast pace environment and work under pressure