Senior Digital IC Physical Design Engineer (PPA/Signoff)

Bitmain; Singapore; Presencial; SGD 120.000 - 180.000; Jornada completa

Descripción de la vacante

Bitmain in Singapore seeks a senior digital IC design engineer to drive physical implementation from RTL to GDS and to sign off critical timing with SPICE analyses. You will shape STA standards, develop robust flows for PR/PV/PI/STA, and support advanced technology nodes and EDA tools.

Experience with yield, PPA, and tape-outs is advantageous. Strong scripting skills and familiarity with 3D IC design are valued, along with hands-on use of industry tools such as Calibre, INVS, FC, PT, PX, and RH.

Formación

• Experience in complete digital physical design flow from RTL to GDS.
• Strong STA analysis methods and signoff standards for advanced nodes.
• Familiarity with PPA, yield optimization, and related tool development.
• Tape-out experience with ultra-low-voltage or complex IP chips is a plus.

Responsabilidades

• Responsible for digital circuit physical implementation (RTL to GDS) and PV/PI/STA signoff.
• Perform full-chip STA signoff and SPICE simulations for critical paths.
• Develop and optimize PR/PV/PI/STA design flows; support advanced nodes and EDA tools.

Conocimientos

Digital physical design flow

STA analysis

Scripting/programming

3D IC design familiarity

Power/area optimization

Herramientas

INVS

FC

Calibre

DC/FC synthesis

Python

Descripción del empleo

Bitmain in Singapore seeks a senior digital IC design engineer to drive physical implementation from RTL to GDS and to sign off critical timing with SPICE analyses. You will shape STA standards, develop robust flows for PR/PV/PI/STA, and support advanced technology nodes and EDA tools.

Experience with yield, PPA, and tape-outs is advantageous. Strong scripting skills and familiarity with 3D IC design are valued, along with hands-on use of industry tools such as Calibre, INVS, FC, PT, PX, and RH.