Physical Design Engineer

BITMAIN; Singapore; On-site; SGD 120,000 - 180,000; Full time

Job summary

Bitmain in Singapore seeks a senior digital IC design engineer to drive physical implementation from RTL to GDS and to sign off critical timing with SPICE analyses. You will shape STA standards, develop robust flows for PR/PV/PI/STA, and support advanced technology nodes and EDA tools.

Experience with yield, PPA, and tape-outs is advantageous. Strong scripting skills and familiarity with 3D IC design are valued, along with hands-on use of industry tools such as Calibre, INVS, FC, PT, PX, and RH.

Qualifications

• Experience in complete digital physical design flow from RTL to GDS.
• Strong STA analysis methods and signoff standards for advanced nodes.
• Familiarity with PPA, yield optimization, and related tool development.
• Tape-out experience with ultra-low-voltage or complex IP chips is a plus.

Responsibilities

• Responsible for digital circuit physical implementation (RTL to GDS) and PV/PI/STA signoff.
• Perform full-chip STA signoff and SPICE simulations for critical paths.
• Develop and optimize PR/PV/PI/STA design flows; support advanced nodes and EDA tools.

Skills

Digital physical design flow

STA analysis

Scripting/programming

3D IC design familiarity

Power/area optimization

Tools

INVS

FC

Calibre

DC/FC synthesis

Python

Job description

Requirement

• 1. Responsible for digital circuit physical implementation (RTL to GDS) and PV/PI signoff; perform full-chip STA signoff, participate in defining STA signoff standards, and conduct SPICE simulation for critical timing paths;
• 2. Develop, optimize, and maintain PR/PV/PI/STA design flows; support the introduction of advanced technology nodes and EDA tools;
• 3. Participate in PPA (Power, Performance, Area) and yield optimization, including related tool development and flow improvement.

• 1. Proficient in the complete digital physical design flow (RTL to GDS) and related EDA tools (INVS, FC, PT, PX, RH, Calibre, etc.); strong expertise in STA analysis methods and flows; familiar with DC or FC synthesis processes;
• 2. Experience in top-level PR/PI/PV/BUMP or ESD planning is a plus; familiarity with signoff standards for advanced process nodes is preferred; proven tape-out experience with ultra-low-voltage, large-scale, or complex IP chips is a strong advantage;
• 3. Familiar with low-power design methodologies and power analysis flows; experience in PPA optimization preferred;
• 4. Strong programming skills in one or more languages such as Tcl, Python, Perl, C, or C++;
• 5. Familiar with 3D IC design; relevant experience is a plus;
• 6. Prior experience with STA signoff in tape-out projects is preferred.